1 | /* Sets (bit vectors) of hard registers, and operations on them. |
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2 | Copyright (C) 1987, 1992, 1994 Free Software Foundation, Inc. |
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3 | |
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4 | This file is part of GNU CC |
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5 | |
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6 | GNU CC is free software; you can redistribute it and/or modify |
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7 | it under the terms of the GNU General Public License as published by |
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8 | the Free Software Foundation; either version 2, or (at your option) |
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9 | any later version. |
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10 | |
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11 | GNU CC is distributed in the hope that it will be useful, |
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12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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14 | GNU General Public License for more details. |
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15 | |
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16 | You should have received a copy of the GNU General Public License |
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17 | along with GNU CC; see the file COPYING. If not, write to |
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18 | the Free Software Foundation, 59 Temple Place - Suite 330, |
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19 | Boston, MA 02111-1307, USA. */ |
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20 | |
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21 | |
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22 | /* Define the type of a set of hard registers. */ |
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23 | |
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24 | /* HARD_REG_ELT_TYPE is a typedef of the unsigned integral type which |
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25 | will be used for hard reg sets, either alone or in an array. |
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26 | |
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27 | If HARD_REG_SET is a macro, its definition is HARD_REG_ELT_TYPE, |
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28 | and it has enough bits to represent all the target machine's hard |
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29 | registers. Otherwise, it is a typedef for a suitably sized array |
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30 | of HARD_REG_ELT_TYPEs. HARD_REG_SET_LONGS is defined as how many. |
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31 | |
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32 | Note that lots of code assumes that the first part of a regset is |
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33 | the same format as a HARD_REG_SET. To help make sure this is true, |
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34 | we only try the widest integer mode (HOST_WIDE_INT) instead of all the |
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35 | smaller types. This approach loses only if there are a very few |
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36 | registers and then only in the few cases where we have an array of |
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37 | HARD_REG_SETs, so it needn't be as complex as it used to be. */ |
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38 | |
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39 | typedef unsigned HOST_WIDE_INT HARD_REG_ELT_TYPE; |
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40 | |
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41 | #if FIRST_PSEUDO_REGISTER <= HOST_BITS_PER_WIDE_INT |
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42 | |
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43 | #define HARD_REG_SET HARD_REG_ELT_TYPE |
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44 | |
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45 | #else |
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46 | |
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47 | #define HARD_REG_SET_LONGS \ |
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48 | ((FIRST_PSEUDO_REGISTER + HOST_BITS_PER_WIDE_INT - 1) \ |
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49 | / HOST_BITS_PER_WIDE_INT) |
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50 | typedef HARD_REG_ELT_TYPE HARD_REG_SET[HARD_REG_SET_LONGS]; |
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51 | |
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52 | #endif |
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53 | |
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54 | /* HARD_CONST is used to cast a constant to the appropriate type |
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55 | for use with a HARD_REG_SET. */ |
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56 | |
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57 | #define HARD_CONST(X) ((HARD_REG_ELT_TYPE) (X)) |
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58 | |
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59 | /* Define macros SET_HARD_REG_BIT, CLEAR_HARD_REG_BIT and TEST_HARD_REG_BIT |
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60 | to set, clear or test one bit in a hard reg set of type HARD_REG_SET. |
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61 | All three take two arguments: the set and the register number. |
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62 | |
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63 | In the case where sets are arrays of longs, the first argument |
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64 | is actually a pointer to a long. |
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65 | |
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66 | Define two macros for initializing a set: |
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67 | CLEAR_HARD_REG_SET and SET_HARD_REG_SET. |
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68 | These take just one argument. |
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69 | |
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70 | Also define macros for copying hard reg sets: |
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71 | COPY_HARD_REG_SET and COMPL_HARD_REG_SET. |
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72 | These take two arguments TO and FROM; they read from FROM |
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73 | and store into TO. COMPL_HARD_REG_SET complements each bit. |
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74 | |
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75 | Also define macros for combining hard reg sets: |
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76 | IOR_HARD_REG_SET and AND_HARD_REG_SET. |
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77 | These take two arguments TO and FROM; they read from FROM |
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78 | and combine bitwise into TO. Define also two variants |
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79 | IOR_COMPL_HARD_REG_SET and AND_COMPL_HARD_REG_SET |
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80 | which use the complement of the set FROM. |
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81 | |
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82 | Also define GO_IF_HARD_REG_SUBSET (X, Y, TO): |
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83 | if X is a subset of Y, go to TO. |
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84 | */ |
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85 | |
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86 | #ifdef HARD_REG_SET |
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87 | |
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88 | #define SET_HARD_REG_BIT(SET, BIT) \ |
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89 | ((SET) |= HARD_CONST (1) << (BIT)) |
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90 | #define CLEAR_HARD_REG_BIT(SET, BIT) \ |
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91 | ((SET) &= ~(HARD_CONST (1) << (BIT))) |
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92 | #define TEST_HARD_REG_BIT(SET, BIT) \ |
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93 | ((SET) & (HARD_CONST (1) << (BIT))) |
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94 | |
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95 | #define CLEAR_HARD_REG_SET(TO) ((TO) = HARD_CONST (0)) |
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96 | #define SET_HARD_REG_SET(TO) ((TO) = ~ HARD_CONST (0)) |
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97 | |
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98 | #define COPY_HARD_REG_SET(TO, FROM) ((TO) = (FROM)) |
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99 | #define COMPL_HARD_REG_SET(TO, FROM) ((TO) = ~(FROM)) |
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100 | |
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101 | #define IOR_HARD_REG_SET(TO, FROM) ((TO) |= (FROM)) |
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102 | #define IOR_COMPL_HARD_REG_SET(TO, FROM) ((TO) |= ~ (FROM)) |
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103 | #define AND_HARD_REG_SET(TO, FROM) ((TO) &= (FROM)) |
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104 | #define AND_COMPL_HARD_REG_SET(TO, FROM) ((TO) &= ~ (FROM)) |
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105 | |
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106 | #define GO_IF_HARD_REG_SUBSET(X,Y,TO) if (HARD_CONST (0) == ((X) & ~(Y))) goto TO |
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107 | |
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108 | #define GO_IF_HARD_REG_EQUAL(X,Y,TO) if ((X) == (Y)) goto TO |
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109 | |
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110 | #else |
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111 | |
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112 | #define UHOST_BITS_PER_WIDE_INT ((unsigned) HOST_BITS_PER_WIDE_INT) |
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113 | |
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114 | #define SET_HARD_REG_BIT(SET, BIT) \ |
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115 | ((SET)[(BIT) / UHOST_BITS_PER_WIDE_INT] \ |
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116 | |= HARD_CONST (1) << ((BIT) % UHOST_BITS_PER_WIDE_INT)) |
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117 | |
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118 | #define CLEAR_HARD_REG_BIT(SET, BIT) \ |
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119 | ((SET)[(BIT) / UHOST_BITS_PER_WIDE_INT] \ |
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120 | &= ~(HARD_CONST (1) << ((BIT) % UHOST_BITS_PER_WIDE_INT))) |
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121 | |
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122 | #define TEST_HARD_REG_BIT(SET, BIT) \ |
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123 | ((SET)[(BIT) / UHOST_BITS_PER_WIDE_INT] \ |
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124 | & (HARD_CONST (1) << ((BIT) % UHOST_BITS_PER_WIDE_INT))) |
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125 | |
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126 | #define CLEAR_HARD_REG_SET(TO) \ |
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127 | do { register HARD_REG_ELT_TYPE *scan_tp_ = (TO); \ |
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128 | register int i; \ |
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129 | for (i = 0; i < HARD_REG_SET_LONGS; i++) \ |
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130 | *scan_tp_++ = 0; } while (0) |
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131 | |
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132 | #define SET_HARD_REG_SET(TO) \ |
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133 | do { register HARD_REG_ELT_TYPE *scan_tp_ = (TO); \ |
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134 | register int i; \ |
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135 | for (i = 0; i < HARD_REG_SET_LONGS; i++) \ |
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136 | *scan_tp_++ = -1; } while (0) |
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137 | |
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138 | #define COPY_HARD_REG_SET(TO, FROM) \ |
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139 | do { register HARD_REG_ELT_TYPE *scan_tp_ = (TO), *scan_fp_ = (FROM); \ |
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140 | register int i; \ |
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141 | for (i = 0; i < HARD_REG_SET_LONGS; i++) \ |
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142 | *scan_tp_++ = *scan_fp_++; } while (0) |
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143 | |
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144 | #define COMPL_HARD_REG_SET(TO, FROM) \ |
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145 | do { register HARD_REG_ELT_TYPE *scan_tp_ = (TO), *scan_fp_ = (FROM); \ |
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146 | register int i; \ |
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147 | for (i = 0; i < HARD_REG_SET_LONGS; i++) \ |
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148 | *scan_tp_++ = ~ *scan_fp_++; } while (0) |
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149 | |
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150 | #define AND_HARD_REG_SET(TO, FROM) \ |
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151 | do { register HARD_REG_ELT_TYPE *scan_tp_ = (TO), *scan_fp_ = (FROM); \ |
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152 | register int i; \ |
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153 | for (i = 0; i < HARD_REG_SET_LONGS; i++) \ |
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154 | *scan_tp_++ &= *scan_fp_++; } while (0) |
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155 | |
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156 | #define AND_COMPL_HARD_REG_SET(TO, FROM) \ |
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157 | do { register HARD_REG_ELT_TYPE *scan_tp_ = (TO), *scan_fp_ = (FROM); \ |
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158 | register int i; \ |
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159 | for (i = 0; i < HARD_REG_SET_LONGS; i++) \ |
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160 | *scan_tp_++ &= ~ *scan_fp_++; } while (0) |
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161 | |
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162 | #define IOR_HARD_REG_SET(TO, FROM) \ |
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163 | do { register HARD_REG_ELT_TYPE *scan_tp_ = (TO), *scan_fp_ = (FROM); \ |
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164 | register int i; \ |
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165 | for (i = 0; i < HARD_REG_SET_LONGS; i++) \ |
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166 | *scan_tp_++ |= *scan_fp_++; } while (0) |
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167 | |
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168 | #define IOR_COMPL_HARD_REG_SET(TO, FROM) \ |
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169 | do { register HARD_REG_ELT_TYPE *scan_tp_ = (TO), *scan_fp_ = (FROM); \ |
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170 | register int i; \ |
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171 | for (i = 0; i < HARD_REG_SET_LONGS; i++) \ |
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172 | *scan_tp_++ |= ~ *scan_fp_++; } while (0) |
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173 | |
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174 | #define GO_IF_HARD_REG_SUBSET(X,Y,TO) \ |
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175 | do { register HARD_REG_ELT_TYPE *scan_xp_ = (X), *scan_yp_ = (Y); \ |
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176 | register int i; \ |
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177 | for (i = 0; i < HARD_REG_SET_LONGS; i++) \ |
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178 | if (0 != (*scan_xp_++ & ~ *scan_yp_++)) break; \ |
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179 | if (i == HARD_REG_SET_LONGS) goto TO; } while (0) |
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180 | |
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181 | #define GO_IF_HARD_REG_EQUAL(X,Y,TO) \ |
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182 | do { register HARD_REG_ELT_TYPE *scan_xp_ = (X), *scan_yp_ = (Y); \ |
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183 | register int i; \ |
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184 | for (i = 0; i < HARD_REG_SET_LONGS; i++) \ |
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185 | if (*scan_xp_++ != *scan_yp_++) break; \ |
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186 | if (i == HARD_REG_SET_LONGS) goto TO; } while (0) |
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187 | |
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188 | #endif |
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189 | |
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190 | /* Define some standard sets of registers. */ |
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191 | |
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192 | /* Indexed by hard register number, contains 1 for registers |
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193 | that are fixed use (stack pointer, pc, frame pointer, etc.). |
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194 | These are the registers that cannot be used to allocate |
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195 | a pseudo reg whose life does not cross calls. */ |
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196 | |
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197 | extern char fixed_regs[FIRST_PSEUDO_REGISTER]; |
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198 | |
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199 | /* The same info as a HARD_REG_SET. */ |
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200 | |
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201 | extern HARD_REG_SET fixed_reg_set; |
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202 | |
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203 | /* Indexed by hard register number, contains 1 for registers |
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204 | that are fixed use or are clobbered by function calls. |
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205 | These are the registers that cannot be used to allocate |
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206 | a pseudo reg whose life crosses calls. */ |
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207 | |
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208 | extern char call_used_regs[FIRST_PSEUDO_REGISTER]; |
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209 | |
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210 | /* The same info as a HARD_REG_SET. */ |
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211 | |
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212 | extern HARD_REG_SET call_used_reg_set; |
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213 | |
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214 | /* Indexed by hard register number, contains 1 for registers that are |
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215 | fixed use -- i.e. in fixed_regs -- or a function value return register |
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216 | or STRUCT_VALUE_REGNUM or STATIC_CHAIN_REGNUM. These are the |
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217 | registers that cannot hold quantities across calls even if we are |
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218 | willing to save and restore them. */ |
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219 | |
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220 | extern char call_fixed_regs[FIRST_PSEUDO_REGISTER]; |
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221 | |
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222 | /* The same info as a HARD_REG_SET. */ |
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223 | |
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224 | extern HARD_REG_SET call_fixed_reg_set; |
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225 | |
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226 | /* Indexed by hard register number, contains 1 for registers |
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227 | that are being used for global register decls. |
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228 | These must be exempt from ordinary flow analysis |
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229 | and are also considered fixed. */ |
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230 | |
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231 | extern char global_regs[FIRST_PSEUDO_REGISTER]; |
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232 | |
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233 | /* Table of register numbers in the order in which to try to use them. */ |
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234 | |
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235 | #ifdef REG_ALLOC_ORDER /* Avoid undef symbol in certain broken linkers. */ |
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236 | extern int reg_alloc_order[FIRST_PSEUDO_REGISTER]; |
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237 | #endif |
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238 | |
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239 | /* For each reg class, a HARD_REG_SET saying which registers are in it. */ |
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240 | |
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241 | extern HARD_REG_SET reg_class_contents[]; |
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242 | |
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243 | /* For each reg class, number of regs it contains. */ |
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244 | |
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245 | extern int reg_class_size[N_REG_CLASSES]; |
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246 | |
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247 | /* For each reg class, table listing all the containing classes. */ |
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248 | |
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249 | extern enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; |
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250 | |
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251 | /* For each reg class, table listing all the classes contained in it. */ |
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252 | |
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253 | extern enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; |
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254 | |
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255 | /* For each pair of reg classes, |
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256 | a largest reg class contained in their union. */ |
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257 | |
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258 | extern enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; |
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259 | |
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260 | /* For each pair of reg classes, |
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261 | the smallest reg class that contains their union. */ |
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262 | |
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263 | extern enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; |
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264 | |
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265 | /* Number of non-fixed registers. */ |
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266 | |
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267 | extern int n_non_fixed_regs; |
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268 | |
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269 | /* Vector indexed by hardware reg giving its name. */ |
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270 | |
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271 | extern char *reg_names[FIRST_PSEUDO_REGISTER]; |
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