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7 | 3.0-CURRENT i386) [Netscape]"> |
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8 | <TITLE>Motorola Oncore GPS Receiver |
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9 | </TITLE> |
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10 | </HEAD> |
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11 | <BODY> |
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12 | |
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13 | <H3> |
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14 | Motorola Oncore GPS receiver</H3> |
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15 | |
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16 | <HR> |
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17 | <H4> |
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18 | Synopsis</H4> |
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19 | |
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20 | Address: 127.127.30.<i>u</i><BR> |
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21 | Reference ID: <TT>GPS</TT><BR> |
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22 | Driver ID: ONCORE<BR> |
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23 | Serial Port: <TT>/dev/oncore.serial.</TT><i>u</i>; 9600 baud, 8-bits, |
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24 | no parity.<BR> |
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25 | PPS Port: <TT>/dev/oncore.pps.</TT><i>u</i>; <TT>PPS_CAPTUREASSERT</TT> |
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26 | required, <TT>PPS_OFFSETASSERT</TT> supported.<BR> |
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27 | Configuration File: <TT>/etc/ntp.oncore<TT><i>u</i> or, |
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28 | <TT>/etc/ntp.oncore.<TT><i>u</i>, or <TT>/etc/ntp.oncore<TT>. |
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29 | <H4> |
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30 | Description</H4> |
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31 | This driver supports most models of the |
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32 | <A HREF="http://www.mot.com/AECS/PNSB/products">Motorola Oncore GPS receivers</A> |
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33 | (Basic, PVT6, VP, UT, UT+, GT, GT+, SL, M12), |
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34 | as long as they support the <I>Motorola Binary Protocol</I>. |
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35 | |
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36 | <P>The three most interesting versions of the Oncore are the VP, |
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37 | the UT+, and the "Remote" which is a prepackaged UT+. |
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38 | The VP is no longer available. |
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39 | The Motorola evaluation kit |
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40 | can also be recommended, it interfaces to a PC straightaway, using the |
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41 | serial (DCD) or parallel port for PPS input and packs the |
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42 | receiver in a nice and sturdy box. |
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43 | Two less expensive interface kits are available from |
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44 | <A HREF="http://www.tapr.org">TAPR</A>. |
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45 | |
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46 | <BR> |
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47 | <CENTER><TABLE NOSAVE > |
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48 | <TR NOSAVE> |
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49 | <TD NOSAVE><IMG SRC="pic/oncore_utplusbig.gif" HEIGHT=124 |
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50 | WIDTH=210></TD> |
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51 | |
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52 | <TD><IMG SRC="pic/oncore_evalbig.gif" HEIGHT=124 WIDTH=182></TD> |
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53 | |
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54 | <TD><IMG SRC="pic/oncore_remoteant.jpg" HEIGHT=188 WIDTH=178></TD> |
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55 | </TR> |
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56 | |
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57 | <TR> |
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58 | <TD> |
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59 | <CENTER>UT+ oncore</CENTER> |
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60 | </TD> |
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61 | |
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62 | <TD> |
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63 | <CENTER>Evaluation kit</CENTER> |
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64 | </TD> |
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65 | |
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66 | <TD> |
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67 | <CENTER>Oncore Remote</CENTER> |
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68 | </TD> |
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69 | </TR> |
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70 | </TABLE></CENTER> |
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71 | |
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72 | <P>The driver requires a standard <TT>PPS</TT> interface for the |
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73 | pulse-per-second output from the receiver. The serial data stream alone |
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74 | does not provide precision time stamps (0-50msec variance, according to |
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75 | the manual), whereas the PPS output is precise down to 50 nsec (1 sigma) |
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76 | for the VP/UT models. |
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77 | If you do not have the PPS signal available, then you should probably be using |
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78 | the NMEA driver rather than the Oncore driver. |
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79 | |
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80 | <P>The driver will use the "position hold" mode with |
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81 | user provided coordinates, |
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82 | the receivers built-in site-survey, |
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83 | or a similar algorithm implemented in this driver to determine the antenna position. |
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84 | <H4> |
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85 | Monitor Data</H4> |
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86 | The driver always puts a lot of useful information on the clockstats file, |
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87 | and when run with debugging can be quite chatty on stdout. |
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88 | When first starting to use the driver you should definitely review the information |
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89 | written to the clockstats file to verify that the driver is running correctly. |
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90 | <P> |
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91 | In addition, on platforms supporting Shared Memory, all of the messages |
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92 | received from the Oncore receiver are made available in shared memory for |
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93 | use by other programs. |
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94 | See the <A HREF=Oncore-SHMEM.htm> Oncore-SHMEM </A> manual page for |
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95 | information on how to use this option. |
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96 | For either debugging or using the SHMEM option, an Oncore Reference Manual |
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97 | for the specific receiver in use will be required. |
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98 | <H4> |
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99 | Fudge Factors</H4> |
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100 | |
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101 | <DL> |
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102 | <DT> |
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103 | <TT>time1 <I>time</I></TT></DT> |
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104 | |
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105 | <DD> |
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106 | Specifies the time offset calibration factor, in seconds and fraction, |
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107 | with default 0.0.</DD> |
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108 | |
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109 | <DT> |
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110 | <TT>time2 <I>time</I></TT></DT> |
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111 | |
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112 | <DD> |
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113 | Not used by this driver.</DD> |
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114 | |
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115 | <DT> |
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116 | <TT>stratum <I>number</I></TT></DT> |
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117 | |
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118 | <DD> |
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119 | Specifies the driver stratum, in decimal from 0 to 15, with default |
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120 | 0.</DD> |
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121 | |
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122 | <DT> |
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123 | <TT>refid <I>string</I></TT></DT> |
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124 | |
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125 | <DD> |
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126 | Specifies the driver reference identifier, an ASCII string from one to |
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127 | four characters, with default <TT>GPS</TT>.</DD> |
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128 | |
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129 | <DT> |
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130 | <TT>flag1 0 | 1</TT></DT> |
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131 | |
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132 | <DD> |
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133 | Not used by this driver.</DD> |
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134 | |
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135 | <DT> |
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136 | <TT>flag2 0 | 1</TT></DT> |
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137 | |
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138 | <DD> |
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139 | Not used by this driver.</DD> |
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140 | |
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141 | <DT> |
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142 | <TT>flag3 0 | 1</TT></DT> |
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143 | |
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144 | <DD> |
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145 | Not used by this driver.</DD> |
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146 | |
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147 | <DT> |
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148 | <TT>flag4 0 | 1</TT></DT> |
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149 | |
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150 | <DD> |
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151 | Not used by this driver.</DD> |
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152 | </DL> |
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153 | <B>Additional Information</B> |
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154 | <P>The driver was initially developed on FreeBSD, and has since been tested |
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155 | on Linux, SunOS and Solaris. |
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156 | <P><B>Configuration</B> |
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157 | <P>There is a driver specific configuration file <TT>/etc/ntp.oncore</TT> |
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158 | that contains information on the startup mode, the location of the GPS |
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159 | receiver, an offset of the PPS signal from zero, and the cable delay. |
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160 | The offset shifts the PPS signal to avoid interrupt pileups `on' the second, |
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161 | and adjust the timestamp accordingly. |
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162 | See the driver source for information on this file. |
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163 | The default with no file is: no delay, no offset, and a site survey is done |
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164 | to get the location of the gps receiver. |
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165 | |
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166 | <P>The <TT>/etc/ntp.conf</TT> file will need a line of the form<BR> |
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167 | |
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168 | <TT> pps /dev/oncore.pps.0 [ assert/clear ] hardpps</TT><BR> |
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169 | if you want the oncore driver to control the kernel PLL. |
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170 | For more information, see the <A HREF=clockopt.htm>Reference Clock |
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171 | Options</A> page. |
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172 | |
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173 | <P><B>Performance</B> |
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174 | <P>Really good. With the VP/UT+, the generated PPS pulse is referenced |
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175 | to UTC(GPS) with better than 50 nsec (1 sigma) accuracy. The |
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176 | limiting factor will be the timebase of the computer and the precision |
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177 | with which you can timestamp the rising flank of the |
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178 | PPS signal. |
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179 | Using FreeBSD, a FPGA based Timecounter/PPS interface, |
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180 | and an ovenized quartz oscillator, that performance has been reproduced. |
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181 | For more details on this aspect: <A |
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182 | HREF="http://phk.freebsd.dk/rover.html">Sub-Microsecond |
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183 | timekeeping under FreeBSD</A>. |
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184 | <HR> |
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185 | <ADDRESS> |
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186 | Poul-Henning Kamp (phk@FreeBSD.org), |
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187 | Reg Clemens (reg@dwf.com) |
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188 | </ADDRESS> |
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189 | </BODY> |
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190 | </HTML> |
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