[8833] | 1 | 3. When find_reloads is used to count number of spills needed |
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| 2 | it does not take into account the fact that a reload may |
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| 3 | turn out to be a dummy. |
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| 4 | |
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| 5 | I'm not sure this really happens any more. Doesn't it find |
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| 6 | all the dummies on both passes? |
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| 7 | |
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| 8 | 10. movl a3@,a0 |
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| 9 | movl a3@(16),a1 |
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| 10 | clrb a0@(a1:l) |
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| 11 | is generated and may be worse than |
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| 12 | movl a3@,a0 |
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| 13 | addl a3@(16),a0 |
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| 14 | clrb a0@ |
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| 15 | If ordering of operands is improved, many more |
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| 16 | such cases will be generated from typical array accesses. |
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| 17 | |
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| 18 | 38. Hack expand_mult so that if there is no same-modes multiply |
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| 19 | it will use a widening multiply and then truncate rather than |
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| 20 | calling the library. |
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| 21 | |
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| 22 | 39. Hack expanding of division to notice cases for |
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| 23 | long -> short division. |
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| 24 | |
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| 25 | 40. Represent divide insns as (DIV:SI ...) followed by |
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| 26 | a separate lowpart extract. Represent remainder insns as DIV:SI |
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| 27 | followed by a separate highpart extract. Then cse can work on |
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| 28 | the DIV:SI part. Problem is, this may not be desirable on machines |
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| 29 | where computing the quotient alone does not necessarily give |
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| 30 | a remainder--such as the 68020 for long operands. |
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| 31 | |
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| 32 | 52. Reloading can look at how reload_contents got set up. |
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| 33 | If it was copied from a register, just reload from that register. |
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| 34 | Otherwise, perhaps can change the previous insn to move the |
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| 35 | data via the reload reg, thus avoiding one memory ref. |
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| 36 | |
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| 37 | 63. Potential problem in cc_status.value2, if it ever activates itself |
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| 38 | after a two-address subtraction (which currently cannot happen). |
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| 39 | It is supposed to compare the current value of the destination |
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| 40 | but eliminating it would use the results of the subtraction, equivalent |
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| 41 | to comparing the previous value of the destination. |
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| 42 | |
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| 43 | 65. Should loops that neither start nor end with a break |
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| 44 | be rearranged to end with the last break? |
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| 45 | |
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| 46 | 69. Define the floating point converting arithmetic instructions |
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| 47 | for the 68881. |
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| 48 | |
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| 49 | 74. Combine loop opt with cse opt in one pass. Do cse on each loop, |
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| 50 | then loop opt on that loop, and go from innermost loops outward. |
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| 51 | Make loop invariants available for cse at end of loop. |
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| 52 | |
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| 53 | 85. pea can force a value to be reloaded into an areg |
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| 54 | which can make it worse than separate adding and pushing. |
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| 55 | This can only happen for adding something within addql range |
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| 56 | and it only loses if the qty becomes dead at that point |
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| 57 | so it can be added to with no copying. |
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| 58 | |
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| 59 | 93. If a pseudo doesn't get a hard reg everywhere, |
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| 60 | can it get one during a loop? |
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| 61 | |
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| 62 | 96. Can do SImode bitfield insns without reloading, but must |
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| 63 | alter the operands in special ways. |
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| 64 | |
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| 65 | 99. final could check loop-entry branches to see if they |
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| 66 | screw up deletion of a test instruction. If they do, |
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| 67 | can put another test instruction before the branch and |
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| 68 | make it conditional and redirect it. |
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| 69 | |
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| 70 | 106. Aliasing may be impossible if data types of refs differ |
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| 71 | and data type of containing objects also differ. |
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| 72 | (But check this wrt unions.) |
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| 73 | |
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| 74 | 108. Can speed up flow analysis by making a table saying which |
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| 75 | register is set and which registers are used by each instruction that |
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| 76 | only sets one register and only uses two. This way avoid the tree |
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| 77 | walk for such instructions (most instructions). |
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| 78 | |
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| 79 | 109. It is desirable to avoid converting INDEX to SImode if a |
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| 80 | narrower mode suffices, as HImode does on the 68000. |
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| 81 | How can this be done? |
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| 82 | |
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| 83 | 110. Possible special combination pattern: |
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| 84 | If the two operands to a comparison die there and both come from insns |
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| 85 | that are identical except for replacing one operand with the other, |
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| 86 | throw away those insns. Ok if insns being discarded are known 1 to 1. |
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| 87 | An andl #1 after a seq is 1 to 1, but how should compiler know that? |
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| 88 | |
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| 89 | 112. Can convert float to unsigned int by subtracting a constant, |
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| 90 | converting to signed int, and changing the sign bit. |
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| 91 | |
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| 92 | 117. Any number of slow zero-extensions in one loop, that have |
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| 93 | their clr insns moved out of the loop, can share one register |
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| 94 | if their original life spans are disjoint. |
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| 95 | But it may be hard to be sure of this since |
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| 96 | the life span data that regscan produces may be hard to interpret |
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| 97 | validly or may be incorrect after cse. |
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| 98 | |
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| 99 | 118. In cse, when a bfext insn refers to a register, if the field |
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| 100 | corresponds to a halfword or a byte and the register is equivalent |
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| 101 | to a memory location, it would be possible to detect this and |
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| 102 | replace it with a simple memory reference. |
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| 103 | |
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| 104 | 121. Insns that store two values cannot be moved out of loops. |
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| 105 | The code in scan_loop doesn't even try to deal with them. |
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| 106 | |
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| 107 | 122. When insn-output.c turns a bit-test into a sign-test, |
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| 108 | it should see whether the cc is already set up with that sign. |
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| 109 | |
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| 110 | 123. When a conditional expression is used as a function arg, it would |
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| 111 | be faster (and in some cases shorter) to push each alternative rather |
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| 112 | than compute in a register and push that. This would require |
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| 113 | being able to specify "push this" as a target for expand_expr. |
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| 114 | |
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| 115 | 124. On the 386, bad code results from foo (bar ()) when bar |
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| 116 | returns a double, because the pseudo used fails to get preferenced |
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| 117 | into an fp reg because of the distinction between regs 8 and 9. |
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