1 | /* Definitions of target machine for GNU compiler, for Intel 80960 |
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2 | Copyright (C) 1992, 1993, 1995 Free Software Foundation, Inc. |
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3 | Contributed by Steven McGeady, Intel Corp. |
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4 | Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson |
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5 | Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support. |
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6 | |
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7 | This file is part of GNU CC. |
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8 | |
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9 | GNU CC is free software; you can redistribute it and/or modify |
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10 | it under the terms of the GNU General Public License as published by |
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11 | the Free Software Foundation; either version 2, or (at your option) |
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12 | any later version. |
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13 | |
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14 | GNU CC is distributed in the hope that it will be useful, |
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15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
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16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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17 | GNU General Public License for more details. |
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18 | |
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19 | You should have received a copy of the GNU General Public License |
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20 | along with GNU CC; see the file COPYING. If not, write to |
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21 | the Free Software Foundation, 59 Temple Place - Suite 330, |
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22 | Boston, MA 02111-1307, USA. */ |
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23 | |
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24 | /* Note that some other tm.h files may include this one and then override |
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25 | many of the definitions that relate to assembler syntax. */ |
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26 | |
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27 | /* Names to predefine in the preprocessor for this target machine. */ |
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28 | #define CPP_PREDEFINES "-Di960 -Di80960 -DI960 -DI80960 -Acpu(i960) -Amachine(i960)" |
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29 | |
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30 | /* Name to predefine in the preprocessor for processor variations. */ |
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31 | #define CPP_SPEC "%{mic*:-D__i960\ |
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32 | %{mka:-D__i960KA}%{mkb:-D__i960KB}\ |
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33 | %{msa:-D__i960SA}%{msb:-D__i960SB}\ |
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34 | %{mmc:-D__i960MC}\ |
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35 | %{mca:-D__i960CA}%{mcc:-D__i960CC}\ |
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36 | %{mcf:-D__i960CF}}\ |
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37 | %{mka:-D__i960KA__ -D__i960_KA__}\ |
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38 | %{mkb:-D__i960KB__ -D__i960_KB__}\ |
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39 | %{msa:-D__i960SA__ -D__i960_SA__}\ |
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40 | %{msb:-D__i960SB__ -D__i960_SB__}\ |
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41 | %{mmc:-D__i960MC__ -D__i960_MC__}\ |
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42 | %{mca:-D__i960CA__ -D__i960_CA__}\ |
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43 | %{mcc:-D__i960CC__ -D__i960_CC__}\ |
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44 | %{mcf:-D__i960CF__ -D__i960_CF__}\ |
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45 | %{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:\ |
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46 | %{!mcc:%{!mcf:-D__i960_KB -D__i960KB__ %{mic*:-D__i960KB}}}}}}}}}" |
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47 | |
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48 | /* -mic* options make characters signed by default. */ |
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49 | /* Use #if rather than ?: because MIPS C compiler rejects ?: in |
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50 | initializers. */ |
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51 | #if DEFAULT_SIGNED_CHAR |
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52 | #define SIGNED_CHAR_SPEC "%{funsigned-char:-D__CHAR_UNSIGNED__}" |
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53 | #else |
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54 | #define SIGNED_CHAR_SPEC "%{!fsigned-char:%{!mic*:-D__CHAR_UNSIGNED__}}" |
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55 | #endif |
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56 | |
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57 | /* Specs for the compiler, to handle processor variations. |
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58 | If the user gives an explicit -gstabs or -gcoff option, then do not |
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59 | try to add an implicit one, as this will fail. */ |
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60 | #define CC1_SPEC \ |
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61 | "%{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:-mkb}}}}}}}}\ |
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62 | %{!gs*:%{!gc*:%{mbout:%{g*:-gstabs}}\ |
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63 | %{mcoff:%{g*:-gcoff}}\ |
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64 | %{!mbout:%{!mcoff:%{g*:-gstabs}}}}}" |
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65 | |
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66 | /* Specs for the assembler, to handle processor variations. |
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67 | For compatibility with Intel's gnu960 tool chain, pass -A options to |
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68 | the assembler. */ |
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69 | #define ASM_SPEC \ |
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70 | "%{mka:-AKA}%{mkb:-AKB}%{msa:-ASA}%{msb:-ASB}\ |
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71 | %{mmc:-AMC}%{mca:-ACA}%{mcc:-ACC}%{mcf:-ACF}\ |
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72 | %{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:-AKB}}}}}}}}\ |
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73 | %{mlink-relax:-linkrelax}" |
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74 | |
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75 | /* Specs for the linker, to handle processor variations. |
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76 | For compatibility with Intel's gnu960 tool chain, pass -F and -A options |
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77 | to the linker. */ |
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78 | #define LINK_SPEC \ |
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79 | "%{mka:-AKA}%{mkb:-AKB}%{msa:-ASA}%{msb:-ASB}\ |
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80 | %{mmc:-AMC}%{mca:-ACA}%{mcc:-ACC}%{mcf:-ACF}\ |
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81 | %{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:-AKB}}}}}}}}\ |
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82 | %{mbout:-Fbout}%{mcoff:-Fcoff}\ |
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83 | %{mlink-relax:-relax}" |
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84 | |
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85 | /* Specs for the libraries to link with, to handle processor variations. |
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86 | Compatible with Intel's gnu960 tool chain. */ |
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87 | #define LIB_SPEC "%{!nostdlib:-lcg %{p:-lprof}%{pg:-lgprof}\ |
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88 | %{mka:-lfpg}%{msa:-lfpg}%{mca:-lfpg}%{mcf:-lfpg} -lgnu}" |
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89 | |
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90 | /* Show we can debug even without a frame pointer. */ |
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91 | #define CAN_DEBUG_WITHOUT_FP |
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92 | |
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93 | /* Do leaf procedure and tail call optimizations for -O2 and higher. */ |
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94 | #define OPTIMIZATION_OPTIONS(LEVEL) \ |
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95 | { \ |
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96 | if ((LEVEL) >= 2) \ |
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97 | { \ |
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98 | target_flags |= TARGET_FLAG_LEAFPROC; \ |
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99 | target_flags |= TARGET_FLAG_TAILCALL; \ |
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100 | } \ |
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101 | } |
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102 | |
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103 | /* Print subsidiary information on the compiler version in use. */ |
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104 | #define TARGET_VERSION fprintf (stderr," (intel 80960)"); |
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105 | |
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106 | /* Generate DBX debugging information. */ |
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107 | #define DBX_DEBUGGING_INFO |
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108 | |
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109 | /* Generate SDB style debugging information. */ |
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110 | #define SDB_DEBUGGING_INFO |
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111 | |
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112 | /* Generate DBX_DEBUGGING_INFO by default. */ |
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113 | #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG |
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114 | |
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115 | /* Redefine this to print in hex and adjust values like GNU960. The extra |
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116 | bit is used to handle the type long double. Gcc does not support long |
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117 | double in sdb output, but we do support the non-standard format. */ |
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118 | #define PUT_SDB_TYPE(A) \ |
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119 | fprintf (asm_out_file, "\t.type\t0x%x;", (A & 0xf) + 2 * (A & ~0xf)) |
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120 | |
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121 | /* Handle pragmas for compatibility with Intel's compilers. */ |
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122 | #define HANDLE_PRAGMA(FILE) process_pragma (FILE) |
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123 | |
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124 | /* Run-time compilation parameters selecting different hardware subsets. */ |
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125 | |
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126 | /* 960 architecture with floating-point. */ |
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127 | #define TARGET_FLAG_NUMERICS 0x01 |
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128 | #define TARGET_NUMERICS (target_flags & TARGET_FLAG_NUMERICS) |
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129 | |
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130 | /* 960 architecture with memory management. */ |
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131 | /* ??? Not used currently. */ |
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132 | #define TARGET_FLAG_PROTECTED 0x02 |
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133 | #define TARGET_PROTECTED (target_flags & TARGET_FLAG_PROTECTED) |
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134 | |
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135 | /* The following three are mainly used to provide a little sanity checking |
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136 | against the -mARCH flags given. */ |
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137 | |
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138 | /* Nonzero if we should generate code for the KA and similar processors. |
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139 | No FPU, no microcode instructions. */ |
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140 | #define TARGET_FLAG_K_SERIES 0x04 |
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141 | #define TARGET_K_SERIES (target_flags & TARGET_FLAG_K_SERIES) |
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142 | |
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143 | /* Nonzero if we should generate code for the MC processor. |
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144 | Not really different from KB for our purposes. */ |
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145 | #define TARGET_FLAG_MC 0x08 |
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146 | #define TARGET_MC (target_flags & TARGET_FLAG_MC) |
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147 | |
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148 | /* Nonzero if we should generate code for the CA processor. |
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149 | Enables different optimization strategies. */ |
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150 | #define TARGET_FLAG_C_SERIES 0x10 |
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151 | #define TARGET_C_SERIES (target_flags & TARGET_FLAG_C_SERIES) |
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152 | |
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153 | /* Nonzero if we should generate leaf-procedures when we find them. |
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154 | You may not want to do this because leaf-proc entries are |
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155 | slower when not entered via BAL - this would be true when |
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156 | a linker not supporting the optimization is used. */ |
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157 | #define TARGET_FLAG_LEAFPROC 0x20 |
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158 | #define TARGET_LEAFPROC (target_flags & TARGET_FLAG_LEAFPROC) |
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159 | |
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160 | /* Nonzero if we should perform tail-call optimizations when we find them. |
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161 | You may not want to do this because the detection of cases where |
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162 | this is not valid is not totally complete. */ |
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163 | #define TARGET_FLAG_TAILCALL 0x40 |
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164 | #define TARGET_TAILCALL (target_flags & TARGET_FLAG_TAILCALL) |
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165 | |
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166 | /* Nonzero if use of a complex addressing mode is a win on this implementation. |
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167 | Complex addressing modes are probably not worthwhile on the K-series, |
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168 | but they definitely are on the C-series. */ |
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169 | #define TARGET_FLAG_COMPLEX_ADDR 0x80 |
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170 | #define TARGET_COMPLEX_ADDR (target_flags & TARGET_FLAG_COMPLEX_ADDR) |
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171 | |
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172 | /* Align code to 8 byte boundaries for faster fetching. */ |
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173 | #define TARGET_FLAG_CODE_ALIGN 0x100 |
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174 | #define TARGET_CODE_ALIGN (target_flags & TARGET_FLAG_CODE_ALIGN) |
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175 | |
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176 | /* Append branch prediction suffixes to branch opcodes. */ |
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177 | /* ??? Not used currently. */ |
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178 | #define TARGET_FLAG_BRANCH_PREDICT 0x200 |
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179 | #define TARGET_BRANCH_PREDICT (target_flags & TARGET_FLAG_BRANCH_PREDICT) |
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180 | |
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181 | /* Forces prototype and return promotions. */ |
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182 | /* ??? This does not work. */ |
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183 | #define TARGET_FLAG_CLEAN_LINKAGE 0x400 |
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184 | #define TARGET_CLEAN_LINKAGE (target_flags & TARGET_FLAG_CLEAN_LINKAGE) |
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185 | |
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186 | /* For compatibility with iC960 v3.0. */ |
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187 | #define TARGET_FLAG_IC_COMPAT3_0 0x800 |
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188 | #define TARGET_IC_COMPAT3_0 (target_flags & TARGET_FLAG_IC_COMPAT3_0) |
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189 | |
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190 | /* For compatibility with iC960 v2.0. */ |
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191 | #define TARGET_FLAG_IC_COMPAT2_0 0x1000 |
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192 | #define TARGET_IC_COMPAT2_0 (target_flags & TARGET_FLAG_IC_COMPAT2_0) |
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193 | |
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194 | /* If no unaligned accesses are to be permitted. */ |
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195 | #define TARGET_FLAG_STRICT_ALIGN 0x2000 |
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196 | #define TARGET_STRICT_ALIGN (target_flags & TARGET_FLAG_STRICT_ALIGN) |
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197 | |
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198 | /* For compatibility with iC960 assembler. */ |
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199 | #define TARGET_FLAG_ASM_COMPAT 0x4000 |
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200 | #define TARGET_ASM_COMPAT (target_flags & TARGET_FLAG_ASM_COMPAT) |
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201 | |
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202 | /* For compatibility with the gcc960 v1.2 compiler. Use the old structure |
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203 | alignment rules. Also, turns on STRICT_ALIGNMENT. */ |
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204 | #define TARGET_FLAG_OLD_ALIGN 0x8000 |
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205 | #define TARGET_OLD_ALIGN (target_flags & TARGET_FLAG_OLD_ALIGN) |
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206 | |
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207 | extern int target_flags; |
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208 | |
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209 | /* Macro to define tables used to set the flags. |
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210 | This is a list in braces of pairs in braces, |
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211 | each pair being { "NAME", VALUE } |
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212 | where VALUE is the bits to set or minus the bits to clear. |
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213 | An empty string NAME is used to identify the default VALUE. */ |
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214 | |
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215 | /* ??? Not all ten of these architecture variations actually exist, but I |
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216 | am not sure which are real and which aren't. */ |
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217 | |
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218 | #define TARGET_SWITCHES \ |
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219 | { {"sa", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\ |
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220 | {"sb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \ |
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221 | TARGET_FLAG_COMPLEX_ADDR)},\ |
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222 | /* {"sc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\ |
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223 | TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},*/ \ |
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224 | {"ka", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\ |
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225 | {"kb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \ |
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226 | TARGET_FLAG_COMPLEX_ADDR)},\ |
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227 | /* {"kc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\ |
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228 | TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},*/ \ |
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229 | {"mc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\ |
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230 | TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},\ |
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231 | {"ca", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\ |
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232 | TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR)},\ |
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233 | /* {"cb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_C_SERIES|\ |
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234 | TARGET_FLAG_BRANCH_PREDICT|TARGET_FLAG_CODE_ALIGN)},\ |
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235 | {"cc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\ |
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236 | TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\ |
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237 | TARGET_FLAG_CODE_ALIGN)}, */ \ |
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238 | {"cf", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\ |
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239 | TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR)},\ |
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240 | {"numerics", (TARGET_FLAG_NUMERICS)}, \ |
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241 | {"soft-float", -(TARGET_FLAG_NUMERICS)}, \ |
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242 | {"leaf-procedures", TARGET_FLAG_LEAFPROC}, \ |
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243 | {"no-leaf-procedures",-(TARGET_FLAG_LEAFPROC)}, \ |
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244 | {"tail-call",TARGET_FLAG_TAILCALL}, \ |
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245 | {"no-tail-call",-(TARGET_FLAG_TAILCALL)}, \ |
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246 | {"complex-addr",TARGET_FLAG_COMPLEX_ADDR}, \ |
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247 | {"no-complex-addr",-(TARGET_FLAG_COMPLEX_ADDR)}, \ |
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248 | {"code-align",TARGET_FLAG_CODE_ALIGN}, \ |
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249 | {"no-code-align",-(TARGET_FLAG_CODE_ALIGN)}, \ |
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250 | {"clean-linkage", (TARGET_FLAG_CLEAN_LINKAGE)}, \ |
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251 | {"no-clean-linkage", -(TARGET_FLAG_CLEAN_LINKAGE)}, \ |
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252 | {"ic-compat", TARGET_FLAG_IC_COMPAT2_0}, \ |
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253 | {"ic2.0-compat", TARGET_FLAG_IC_COMPAT2_0}, \ |
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254 | {"ic3.0-compat", TARGET_FLAG_IC_COMPAT3_0}, \ |
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255 | {"asm-compat",TARGET_FLAG_ASM_COMPAT}, \ |
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256 | {"intel-asm",TARGET_FLAG_ASM_COMPAT}, \ |
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257 | {"strict-align", TARGET_FLAG_STRICT_ALIGN}, \ |
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258 | {"no-strict-align", -(TARGET_FLAG_STRICT_ALIGN)}, \ |
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259 | {"old-align", (TARGET_FLAG_OLD_ALIGN|TARGET_FLAG_STRICT_ALIGN)}, \ |
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260 | {"no-old-align", -(TARGET_FLAG_OLD_ALIGN|TARGET_FLAG_STRICT_ALIGN)}, \ |
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261 | {"link-relax", 0}, \ |
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262 | {"no-link-relax", 0}, \ |
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263 | { "", TARGET_DEFAULT}} |
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264 | |
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265 | /* Override conflicting target switch options. |
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266 | Doesn't actually detect if more than one -mARCH option is given, but |
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267 | does handle the case of two blatantly conflicting -mARCH options. */ |
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268 | #define OVERRIDE_OPTIONS \ |
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269 | { \ |
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270 | if (TARGET_K_SERIES && TARGET_C_SERIES) \ |
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271 | { \ |
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272 | warning ("conflicting architectures defined - using C series", 0); \ |
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273 | target_flags &= ~TARGET_FLAG_K_SERIES; \ |
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274 | } \ |
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275 | if (TARGET_K_SERIES && TARGET_MC) \ |
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276 | { \ |
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277 | warning ("conflicting architectures defined - using K series", 0); \ |
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278 | target_flags &= ~TARGET_FLAG_MC; \ |
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279 | } \ |
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280 | if (TARGET_C_SERIES && TARGET_MC) \ |
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281 | { \ |
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282 | warning ("conflicting architectures defined - using C series", 0);\ |
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283 | target_flags &= ~TARGET_FLAG_MC; \ |
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284 | } \ |
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285 | if (TARGET_IC_COMPAT3_0) \ |
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286 | { \ |
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287 | flag_short_enums = 1; \ |
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288 | flag_signed_char = 1; \ |
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289 | target_flags |= TARGET_FLAG_CLEAN_LINKAGE; \ |
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290 | if (TARGET_IC_COMPAT2_0) \ |
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291 | { \ |
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292 | warning ("iC2.0 and iC3.0 are incompatible - using iC3.0", 0); \ |
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293 | target_flags &= ~TARGET_FLAG_IC_COMPAT2_0; \ |
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294 | } \ |
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295 | } \ |
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296 | if (TARGET_IC_COMPAT2_0) \ |
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297 | { \ |
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298 | flag_signed_char = 1; \ |
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299 | target_flags |= TARGET_FLAG_CLEAN_LINKAGE; \ |
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300 | } \ |
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301 | i960_initialize (); \ |
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302 | } |
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303 | |
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304 | /* Don't enable anything by default. The user is expected to supply a -mARCH |
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305 | option. If none is given, then -mkb is added by CC1_SPEC. */ |
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306 | #define TARGET_DEFAULT 0 |
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307 | |
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308 | /* Target machine storage layout. */ |
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309 | |
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310 | /* Define for cross-compilation from a host with a different float format |
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311 | or endianness, as well as to support 80 bit long doubles on the i960. */ |
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312 | #define REAL_ARITHMETIC |
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313 | |
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314 | /* Define this if most significant bit is lowest numbered |
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315 | in instructions that operate on numbered bit-fields. */ |
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316 | #define BITS_BIG_ENDIAN 0 |
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317 | |
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318 | /* Define this if most significant byte of a word is the lowest numbered. |
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319 | The i960 case be either big endian or little endian. We only support |
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320 | little endian, which is the most common. */ |
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321 | #define BYTES_BIG_ENDIAN 0 |
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322 | |
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323 | /* Define this if most significant word of a multiword number is lowest |
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324 | numbered. */ |
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325 | #define WORDS_BIG_ENDIAN 0 |
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326 | |
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327 | /* Number of bits in an addressable storage unit. */ |
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328 | #define BITS_PER_UNIT 8 |
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329 | |
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330 | /* Bitfields cannot cross word boundaries. */ |
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331 | #define BITFIELD_NBYTES_LIMITED 1 |
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332 | |
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333 | /* Width in bits of a "word", which is the contents of a machine register. |
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334 | Note that this is not necessarily the width of data type `int'; |
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335 | if using 16-bit ints on a 68000, this would still be 32. |
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336 | But on a machine with 16-bit registers, this would be 16. */ |
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337 | #define BITS_PER_WORD 32 |
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338 | |
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339 | /* Width of a word, in units (bytes). */ |
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340 | #define UNITS_PER_WORD 4 |
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341 | |
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342 | /* Width in bits of a pointer. See also the macro `Pmode' defined below. */ |
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343 | #define POINTER_SIZE 32 |
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344 | |
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345 | /* Width in bits of a long double. Identical to double for now. */ |
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346 | #define LONG_DOUBLE_TYPE_SIZE 64 |
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347 | |
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348 | /* Allocation boundary (in *bits*) for storing pointers in memory. */ |
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349 | #define POINTER_BOUNDARY 32 |
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350 | |
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351 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
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352 | #define PARM_BOUNDARY 32 |
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353 | |
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354 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ |
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355 | #define STACK_BOUNDARY 128 |
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356 | |
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357 | /* Allocation boundary (in *bits*) for the code of a function. */ |
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358 | #define FUNCTION_BOUNDARY 128 |
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359 | |
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360 | /* Alignment of field after `int : 0' in a structure. */ |
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361 | #define EMPTY_FIELD_BOUNDARY 32 |
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362 | |
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363 | /* This makes zero-length anonymous fields lay the next field |
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364 | at a word boundary. It also makes the whole struct have |
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365 | at least word alignment if there are any bitfields at all. */ |
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366 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
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367 | |
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368 | /* Every structure's size must be a multiple of this. */ |
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369 | #define STRUCTURE_SIZE_BOUNDARY 8 |
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370 | |
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371 | /* No data type wants to be aligned rounder than this. |
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372 | Extended precision floats gets 4-word alignment. */ |
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373 | #define BIGGEST_ALIGNMENT 128 |
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374 | |
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375 | /* Define this if move instructions will actually fail to work |
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376 | when given unaligned data. |
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377 | 80960 will work even with unaligned data, but it is slow. */ |
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378 | #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN |
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379 | |
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380 | /* Specify alignment for string literals (which might be higher than the |
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381 | base type's minimal alignment requirement. This allows strings to be |
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382 | aligned on word boundaries, and optimizes calls to the str* and mem* |
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383 | library functions. */ |
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384 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ |
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385 | (TREE_CODE (EXP) == STRING_CST \ |
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386 | && i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) > (ALIGN) \ |
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387 | ? i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) \ |
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388 | : (ALIGN)) |
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389 | |
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390 | /* Make XFmode floating point quantities be 128 bit aligned. */ |
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391 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ |
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392 | (TREE_CODE (TYPE) == ARRAY_TYPE \ |
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393 | && TYPE_MODE (TREE_TYPE (TYPE)) == XFmode \ |
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394 | && (ALIGN) < 128 ? 128 : (ALIGN)) |
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395 | |
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396 | /* Macros to determine size of aggregates (structures and unions |
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397 | in C). Normally, these may be defined to simply return the maximum |
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398 | alignment and simple rounded-up size, but on some machines (like |
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399 | the i960), the total size of a structure is based on a non-trivial |
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400 | rounding method. */ |
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401 | |
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402 | #define ROUND_TYPE_ALIGN(TYPE, COMPUTED, SPECIFIED) \ |
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403 | ((TREE_CODE (TYPE) == REAL_TYPE && TYPE_MODE (TYPE) == XFmode) \ |
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404 | ? 128 /* Put 80 bit floating point elements on 128 bit boundaries. */ \ |
---|
405 | : ((!TARGET_OLD_ALIGN && TREE_CODE (TYPE) == RECORD_TYPE) \ |
---|
406 | ? i960_round_align (MAX ((COMPUTED), (SPECIFIED)), TYPE_SIZE (TYPE)) \ |
---|
407 | : MAX ((COMPUTED), (SPECIFIED)))) |
---|
408 | |
---|
409 | #define ROUND_TYPE_SIZE(TYPE, COMPUTED, SPECIFIED) \ |
---|
410 | ((TREE_CODE (TYPE) == REAL_TYPE && TYPE_MODE (TYPE) == XFmode) \ |
---|
411 | ? build_int_2 (128, 0) : (COMPUTED)) |
---|
412 | |
---|
413 | /* Standard register usage. */ |
---|
414 | |
---|
415 | /* Number of actual hardware registers. |
---|
416 | The hardware registers are assigned numbers for the compiler |
---|
417 | from 0 to just below FIRST_PSEUDO_REGISTER. |
---|
418 | All registers that the compiler knows about must be given numbers, |
---|
419 | even those that are not normally considered general registers. |
---|
420 | |
---|
421 | Registers 0-15 are the global registers (g0-g15). |
---|
422 | Registers 16-31 are the local registers (r0-r15). |
---|
423 | Register 32-35 are the fp registers (fp0-fp3). |
---|
424 | Register 36 is the condition code register. |
---|
425 | Register 37 is unused. */ |
---|
426 | |
---|
427 | #define FIRST_PSEUDO_REGISTER 38 |
---|
428 | |
---|
429 | /* 1 for registers that have pervasive standard uses and are not available |
---|
430 | for the register allocator. On 80960, this includes the frame pointer |
---|
431 | (g15), the previous FP (r0), the stack pointer (r1), the return |
---|
432 | instruction pointer (r2), and the argument pointer (g14). */ |
---|
433 | #define FIXED_REGISTERS \ |
---|
434 | {0, 0, 0, 0, 0, 0, 0, 0, \ |
---|
435 | 0, 0, 0, 0, 0, 0, 1, 1, \ |
---|
436 | 1, 1, 1, 0, 0, 0, 0, 0, \ |
---|
437 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
---|
438 | 0, 0, 0, 0, 1, 1} |
---|
439 | |
---|
440 | /* 1 for registers not available across function calls. |
---|
441 | These must include the FIXED_REGISTERS and also any |
---|
442 | registers that can be used without being saved. |
---|
443 | The latter must include the registers where values are returned |
---|
444 | and the register where structure-value addresses are passed. |
---|
445 | Aside from that, you can include as many other registers as you like. */ |
---|
446 | |
---|
447 | /* On the 80960, note that: |
---|
448 | g0..g3 are used for return values, |
---|
449 | g0..g7 may always be used for parameters, |
---|
450 | g8..g11 may be used for parameters, but are preserved if they aren't, |
---|
451 | g12 is always preserved, but otherwise unused, |
---|
452 | g13 is the struct return ptr if used, or temp, but may be trashed, |
---|
453 | g14 is the leaf return ptr or the arg block ptr otherwise zero, |
---|
454 | must be reset to zero before returning if it was used, |
---|
455 | g15 is the frame pointer, |
---|
456 | r0 is the previous FP, |
---|
457 | r1 is the stack pointer, |
---|
458 | r2 is the return instruction pointer, |
---|
459 | r3-r15 are always available, |
---|
460 | r3 is clobbered by calls in functions that use the arg pointer |
---|
461 | r4-r11 may be clobbered by the mcount call when profiling |
---|
462 | r4-r15 if otherwise unused may be used for preserving global registers |
---|
463 | fp0..fp3 are never available. */ |
---|
464 | #define CALL_USED_REGISTERS \ |
---|
465 | {1, 1, 1, 1, 1, 1, 1, 1, \ |
---|
466 | 0, 0, 0, 0, 0, 1, 1, 1, \ |
---|
467 | 1, 1, 1, 0, 0, 0, 0, 0, \ |
---|
468 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
---|
469 | 1, 1, 1, 1, 1, 1} |
---|
470 | |
---|
471 | /* If no fp unit, make all of the fp registers fixed so that they can't |
---|
472 | be used. */ |
---|
473 | #define CONDITIONAL_REGISTER_USAGE \ |
---|
474 | if (! TARGET_NUMERICS) { \ |
---|
475 | fixed_regs[32] = fixed_regs[33] = fixed_regs[34] = fixed_regs[35] = 1;\ |
---|
476 | } \ |
---|
477 | |
---|
478 | /* Return number of consecutive hard regs needed starting at reg REGNO |
---|
479 | to hold something of mode MODE. |
---|
480 | This is ordinarily the length in words of a value of mode MODE |
---|
481 | but can be less for certain modes in special long registers. |
---|
482 | |
---|
483 | On 80960, ordinary registers hold 32 bits worth, but can be ganged |
---|
484 | together to hold double or extended precision floating point numbers, |
---|
485 | and the floating point registers hold any size floating point number */ |
---|
486 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
---|
487 | ((REGNO) < 32 \ |
---|
488 | ? (((MODE) == VOIDmode) \ |
---|
489 | ? 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \ |
---|
490 | : ((REGNO) < FIRST_PSEUDO_REGISTER) ? 1 : 0) |
---|
491 | |
---|
492 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. |
---|
493 | On 80960, the cpu registers can hold any mode but the float registers |
---|
494 | can only hold SFmode, DFmode, or XFmode. */ |
---|
495 | extern unsigned int hard_regno_mode_ok[FIRST_PSEUDO_REGISTER]; |
---|
496 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
---|
497 | ((hard_regno_mode_ok[REGNO] & (1 << (int) (MODE))) != 0) |
---|
498 | |
---|
499 | /* Value is 1 if it is a good idea to tie two pseudo registers |
---|
500 | when one has mode MODE1 and one has mode MODE2. |
---|
501 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, |
---|
502 | for any hard reg, then this must be 0 for correct output. */ |
---|
503 | |
---|
504 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
---|
505 | ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) |
---|
506 | |
---|
507 | /* Specify the registers used for certain standard purposes. |
---|
508 | The values of these macros are register numbers. */ |
---|
509 | |
---|
510 | /* 80960 pc isn't overloaded on a register that the compiler knows about. */ |
---|
511 | /* #define PC_REGNUM */ |
---|
512 | |
---|
513 | /* Register to use for pushing function arguments. */ |
---|
514 | #define STACK_POINTER_REGNUM 17 |
---|
515 | |
---|
516 | /* Actual top-of-stack address is same as |
---|
517 | the contents of the stack pointer register. */ |
---|
518 | #define STACK_POINTER_OFFSET (-current_function_outgoing_args_size) |
---|
519 | |
---|
520 | /* Base register for access to local variables of the function. */ |
---|
521 | #define FRAME_POINTER_REGNUM 15 |
---|
522 | |
---|
523 | /* Value should be nonzero if functions must have frame pointers. |
---|
524 | Zero means the frame pointer need not be set up (and parms |
---|
525 | may be accessed via the stack pointer) in functions that seem suitable. |
---|
526 | This is computed in `reload', in reload1.c. */ |
---|
527 | /* ??? It isn't clear to me why this is here. Perhaps because of a bug (since |
---|
528 | fixed) in the definition of INITIAL_FRAME_POINTER_OFFSET which would have |
---|
529 | caused this to fail. */ |
---|
530 | #define FRAME_POINTER_REQUIRED (! leaf_function_p ()) |
---|
531 | |
---|
532 | /* C statement to store the difference between the frame pointer |
---|
533 | and the stack pointer values immediately after the function prologue. |
---|
534 | |
---|
535 | Since the stack grows upward on the i960, this must be a negative number. |
---|
536 | This includes the 64 byte hardware register save area and the size of |
---|
537 | the frame. */ |
---|
538 | |
---|
539 | #define INITIAL_FRAME_POINTER_OFFSET(VAR) \ |
---|
540 | do { (VAR) = - (64 + compute_frame_size (get_frame_size ())); } while (0) |
---|
541 | |
---|
542 | /* Base register for access to arguments of the function. */ |
---|
543 | #define ARG_POINTER_REGNUM 14 |
---|
544 | |
---|
545 | /* Register in which static-chain is passed to a function. |
---|
546 | On i960, we use r3. */ |
---|
547 | #define STATIC_CHAIN_REGNUM 19 |
---|
548 | |
---|
549 | /* Functions which return large structures get the address |
---|
550 | to place the wanted value at in g13. */ |
---|
551 | |
---|
552 | #define STRUCT_VALUE_REGNUM 13 |
---|
553 | |
---|
554 | /* The order in which to allocate registers. */ |
---|
555 | |
---|
556 | #define REG_ALLOC_ORDER \ |
---|
557 | { 4, 5, 6, 7, 0, 1, 2, 3, 13, /* g4, g5, g6, g7, g0, g1, g2, g3, g13 */ \ |
---|
558 | 20, 21, 22, 23, 24, 25, 26, 27,/* r4, r5, r6, r7, r8, r9, r10, r11 */ \ |
---|
559 | 28, 29, 30, 31, 19, 8, 9, 10, /* r12, r13, r14, r15, r3, g8, g9, g10 */ \ |
---|
560 | 11, 12, /* g11, g12 */ \ |
---|
561 | 32, 33, 34, 35, /* fp0, fp1, fp2, fp3 */ \ |
---|
562 | /* We can't actually allocate these. */ \ |
---|
563 | 16, 17, 18, 14, 15, 36, 37} /* r0, r1, r2, g14, g15, cc */ |
---|
564 | |
---|
565 | /* Define the classes of registers for register constraints in the |
---|
566 | machine description. Also define ranges of constants. |
---|
567 | |
---|
568 | One of the classes must always be named ALL_REGS and include all hard regs. |
---|
569 | If there is more than one class, another class must be named NO_REGS |
---|
570 | and contain no registers. |
---|
571 | |
---|
572 | The name GENERAL_REGS must be the name of a class (or an alias for |
---|
573 | another name such as ALL_REGS). This is the class of registers |
---|
574 | that is allowed by "g" or "r" in a register constraint. |
---|
575 | Also, registers outside this class are allocated only when |
---|
576 | instructions express preferences for them. |
---|
577 | |
---|
578 | The classes must be numbered in nondecreasing order; that is, |
---|
579 | a larger-numbered class must never be contained completely |
---|
580 | in a smaller-numbered class. |
---|
581 | |
---|
582 | For any two classes, it is very desirable that there be another |
---|
583 | class that represents their union. */ |
---|
584 | |
---|
585 | /* The 80960 has four kinds of registers, global, local, floating point, |
---|
586 | and condition code. The cc register is never allocated, so no class |
---|
587 | needs to be defined for it. */ |
---|
588 | |
---|
589 | enum reg_class { NO_REGS, GLOBAL_REGS, LOCAL_REGS, LOCAL_OR_GLOBAL_REGS, |
---|
590 | FP_REGS, ALL_REGS, LIM_REG_CLASSES }; |
---|
591 | |
---|
592 | /* 'r' includes floating point registers if TARGET_NUMERICS. 'd' never |
---|
593 | does. */ |
---|
594 | #define GENERAL_REGS ((TARGET_NUMERICS) ? ALL_REGS : LOCAL_OR_GLOBAL_REGS) |
---|
595 | |
---|
596 | #define N_REG_CLASSES (int) LIM_REG_CLASSES |
---|
597 | |
---|
598 | /* Give names of register classes as strings for dump file. */ |
---|
599 | |
---|
600 | #define REG_CLASS_NAMES \ |
---|
601 | { "NO_REGS", "GLOBAL_REGS", "LOCAL_REGS", "LOCAL_OR_GLOBAL_REGS", \ |
---|
602 | "FP_REGS", "ALL_REGS" } |
---|
603 | |
---|
604 | /* Define which registers fit in which classes. |
---|
605 | This is an initializer for a vector of HARD_REG_SET |
---|
606 | of length N_REG_CLASSES. */ |
---|
607 | |
---|
608 | #define REG_CLASS_CONTENTS \ |
---|
609 | { {0, 0}, {0x0ffff, 0}, {0xffff0000, 0}, {-1,0}, {0, -1}, {-1,-1}} |
---|
610 | |
---|
611 | /* The same information, inverted: |
---|
612 | Return the class number of the smallest class containing |
---|
613 | reg number REGNO. This could be a conditional expression |
---|
614 | or could index an array. */ |
---|
615 | |
---|
616 | #define REGNO_REG_CLASS(REGNO) \ |
---|
617 | ((REGNO) < 16 ? GLOBAL_REGS \ |
---|
618 | : (REGNO) < 32 ? LOCAL_REGS \ |
---|
619 | : (REGNO) < 36 ? FP_REGS \ |
---|
620 | : NO_REGS) |
---|
621 | |
---|
622 | /* The class value for index registers, and the one for base regs. |
---|
623 | There is currently no difference between base and index registers on the |
---|
624 | i960, but this distinction may one day be useful. */ |
---|
625 | #define INDEX_REG_CLASS LOCAL_OR_GLOBAL_REGS |
---|
626 | #define BASE_REG_CLASS LOCAL_OR_GLOBAL_REGS |
---|
627 | |
---|
628 | /* Get reg_class from a letter such as appears in the machine description. |
---|
629 | 'f' is a floating point register (fp0..fp3) |
---|
630 | 'l' is a local register (r0-r15) |
---|
631 | 'b' is a global register (g0-g15) |
---|
632 | 'd' is any local or global register |
---|
633 | 'r' or 'g' are pre-defined to the class GENERAL_REGS. */ |
---|
634 | /* 'l' and 'b' are probably never used. Note that 'd' and 'r' are *not* |
---|
635 | the same thing, since 'r' may include the fp registers. */ |
---|
636 | #define REG_CLASS_FROM_LETTER(C) \ |
---|
637 | (((C) == 'f') && (TARGET_NUMERICS) ? FP_REGS : ((C) == 'l' ? LOCAL_REGS : \ |
---|
638 | (C) == 'b' ? GLOBAL_REGS : ((C) == 'd' ? LOCAL_OR_GLOBAL_REGS : NO_REGS))) |
---|
639 | |
---|
640 | /* The letters I, J, K, L and M in a register constraint string |
---|
641 | can be used to stand for particular ranges of immediate operands. |
---|
642 | This macro defines what the ranges are. |
---|
643 | C is the letter, and VALUE is a constant value. |
---|
644 | Return 1 if VALUE is in the range specified by C. |
---|
645 | |
---|
646 | For 80960: |
---|
647 | 'I' is used for literal values 0..31 |
---|
648 | 'J' means literal 0 |
---|
649 | 'K' means 0..-31. */ |
---|
650 | |
---|
651 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ |
---|
652 | ((C) == 'I' ? (((unsigned) (VALUE)) <= 31) \ |
---|
653 | : (C) == 'J' ? ((VALUE) == 0) \ |
---|
654 | : (C) == 'K' ? ((VALUE) > -32 && (VALUE) <= 0) \ |
---|
655 | : 0) |
---|
656 | |
---|
657 | /* Similar, but for floating constants, and defining letters G and H. |
---|
658 | Here VALUE is the CONST_DOUBLE rtx itself. |
---|
659 | For the 80960, G is 0.0 and H is 1.0. */ |
---|
660 | |
---|
661 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ |
---|
662 | ((TARGET_NUMERICS) && \ |
---|
663 | (((C) == 'G' && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \ |
---|
664 | || ((C) == 'H' && ((VALUE) == CONST1_RTX (GET_MODE (VALUE)))))) |
---|
665 | |
---|
666 | /* Given an rtx X being reloaded into a reg required to be |
---|
667 | in class CLASS, return the class of reg to actually use. |
---|
668 | In general this is just CLASS; but on some machines |
---|
669 | in some cases it is preferable to use a more restrictive class. */ |
---|
670 | |
---|
671 | /* On 960, can't load constant into floating-point reg except |
---|
672 | 0.0 or 1.0. |
---|
673 | |
---|
674 | Any hard reg is ok as a src operand of a reload insn. */ |
---|
675 | |
---|
676 | #define PREFERRED_RELOAD_CLASS(X,CLASS) \ |
---|
677 | (GET_CODE (X) == REG && REGNO (X) < FIRST_PSEUDO_REGISTER \ |
---|
678 | ? (CLASS) \ |
---|
679 | : ((CLASS) == FP_REGS && CONSTANT_P (X) \ |
---|
680 | && (X) != CONST0_RTX (DFmode) && (X) != CONST1_RTX (DFmode)\ |
---|
681 | && (X) != CONST0_RTX (SFmode) && (X) != CONST1_RTX (SFmode)\ |
---|
682 | ? NO_REGS \ |
---|
683 | : (CLASS) == ALL_REGS ? LOCAL_OR_GLOBAL_REGS : (CLASS))) |
---|
684 | |
---|
685 | #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ |
---|
686 | secondary_reload_class (CLASS, MODE, IN) |
---|
687 | |
---|
688 | /* Return the maximum number of consecutive registers |
---|
689 | needed to represent mode MODE in a register of class CLASS. */ |
---|
690 | /* On 80960, this is the size of MODE in words, |
---|
691 | except in the FP regs, where a single reg is always enough. */ |
---|
692 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
---|
693 | ((CLASS) == FP_REGS ? 1 : HARD_REGNO_NREGS (0, (MODE))) |
---|
694 | |
---|
695 | /* Stack layout; function entry, exit and calling. */ |
---|
696 | |
---|
697 | /* Define this if pushing a word on the stack |
---|
698 | makes the stack pointer a smaller address. */ |
---|
699 | /* #define STACK_GROWS_DOWNWARD */ |
---|
700 | |
---|
701 | /* Define this if the nominal address of the stack frame |
---|
702 | is at the high-address end of the local variables; |
---|
703 | that is, each additional local variable allocated |
---|
704 | goes at a more negative offset in the frame. */ |
---|
705 | /* #define FRAME_GROWS_DOWNWARD */ |
---|
706 | |
---|
707 | /* Offset within stack frame to start allocating local variables at. |
---|
708 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the |
---|
709 | first local allocated. Otherwise, it is the offset to the BEGINNING |
---|
710 | of the first local allocated. |
---|
711 | |
---|
712 | The i960 has a 64 byte register save area, plus possibly some extra |
---|
713 | bytes allocated for varargs functions. */ |
---|
714 | #define STARTING_FRAME_OFFSET 64 |
---|
715 | |
---|
716 | /* If we generate an insn to push BYTES bytes, |
---|
717 | this says how many the stack pointer really advances by. |
---|
718 | On 80960, don't define this because there are no push insns. */ |
---|
719 | /* #define PUSH_ROUNDING(BYTES) BYTES */ |
---|
720 | |
---|
721 | /* Offset of first parameter from the argument pointer register value. */ |
---|
722 | #define FIRST_PARM_OFFSET(FNDECL) 0 |
---|
723 | |
---|
724 | /* When a parameter is passed in a register, no stack space is |
---|
725 | allocated for it. However, when args are passed in the |
---|
726 | stack, space is allocated for every register parameter. */ |
---|
727 | #define MAYBE_REG_PARM_STACK_SPACE 48 |
---|
728 | #define FINAL_REG_PARM_STACK_SPACE(CONST_SIZE, VAR_SIZE) \ |
---|
729 | i960_final_reg_parm_stack_space (CONST_SIZE, VAR_SIZE); |
---|
730 | #define REG_PARM_STACK_SPACE(DECL) i960_reg_parm_stack_space (DECL) |
---|
731 | #define OUTGOING_REG_PARM_STACK_SPACE |
---|
732 | |
---|
733 | /* Keep the stack pointer constant throughout the function. */ |
---|
734 | #define ACCUMULATE_OUTGOING_ARGS |
---|
735 | |
---|
736 | /* Value is 1 if returning from a function call automatically |
---|
737 | pops the arguments described by the number-of-args field in the call. |
---|
738 | FUNDECL is the declaration node of the function (as a tree), |
---|
739 | FUNTYPE is the data type of the function (as a tree), |
---|
740 | or for a library call it is an identifier node for the subroutine name. */ |
---|
741 | |
---|
742 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 |
---|
743 | |
---|
744 | /* Define how to find the value returned by a library function |
---|
745 | assuming the value has mode MODE. */ |
---|
746 | |
---|
747 | #define LIBCALL_VALUE(MODE) gen_rtx ((REG), (MODE), 0) |
---|
748 | |
---|
749 | /* 1 if N is a possible register number for a function value |
---|
750 | as seen by the caller. |
---|
751 | On 80960, returns are in g0..g3 */ |
---|
752 | |
---|
753 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0) |
---|
754 | |
---|
755 | /* 1 if N is a possible register number for function argument passing. |
---|
756 | On 80960, parameters are passed in g0..g11 */ |
---|
757 | |
---|
758 | #define FUNCTION_ARG_REGNO_P(N) ((N) < 12) |
---|
759 | |
---|
760 | /* Perform any needed actions needed for a function that is receiving a |
---|
761 | variable number of arguments. |
---|
762 | |
---|
763 | CUM is as above. |
---|
764 | |
---|
765 | MODE and TYPE are the mode and type of the current parameter. |
---|
766 | |
---|
767 | PRETEND_SIZE is a variable that should be set to the amount of stack |
---|
768 | that must be pushed by the prolog to pretend that our caller pushed |
---|
769 | it. |
---|
770 | |
---|
771 | Normally, this macro will push all remaining incoming registers on the |
---|
772 | stack and set PRETEND_SIZE to the length of the registers pushed. */ |
---|
773 | |
---|
774 | #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \ |
---|
775 | i960_setup_incoming_varargs(&CUM,MODE,TYPE,&PRETEND_SIZE,NO_RTL) |
---|
776 | |
---|
777 | /* Define a data type for recording info about an argument list |
---|
778 | during the scan of that argument list. This data type should |
---|
779 | hold all necessary information about the function itself |
---|
780 | and about the args processed so far, enough to enable macros |
---|
781 | such as FUNCTION_ARG to determine where the next arg should go. |
---|
782 | |
---|
783 | On 80960, this is two integers, which count the number of register |
---|
784 | parameters and the number of stack parameters seen so far. */ |
---|
785 | |
---|
786 | struct cum_args { int ca_nregparms; int ca_nstackparms; }; |
---|
787 | |
---|
788 | #define CUMULATIVE_ARGS struct cum_args |
---|
789 | |
---|
790 | /* Define the number of registers that can hold parameters. |
---|
791 | This macro is used only in macro definitions below and/or i960.c. */ |
---|
792 | #define NPARM_REGS 12 |
---|
793 | |
---|
794 | /* Define how to round to the next parameter boundary. |
---|
795 | This macro is used only in macro definitions below and/or i960.c. */ |
---|
796 | #define ROUND_PARM(X, MULTIPLE_OF) \ |
---|
797 | ((((X) + (MULTIPLE_OF) - 1) / (MULTIPLE_OF)) * MULTIPLE_OF) |
---|
798 | |
---|
799 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
---|
800 | for a call to a function whose data type is FNTYPE. |
---|
801 | For a library call, FNTYPE is 0. |
---|
802 | |
---|
803 | On 80960, the offset always starts at 0; the first parm reg is g0. */ |
---|
804 | |
---|
805 | #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \ |
---|
806 | ((CUM).ca_nregparms = 0, (CUM).ca_nstackparms = 0) |
---|
807 | |
---|
808 | /* Update the data in CUM to advance over an argument |
---|
809 | of mode MODE and data type TYPE. |
---|
810 | CUM should be advanced to align with the data type accessed and |
---|
811 | also the size of that data type in # of regs. |
---|
812 | (TYPE is null for libcalls where that information may not be available.) */ |
---|
813 | |
---|
814 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ |
---|
815 | i960_function_arg_advance(&CUM, MODE, TYPE, NAMED) |
---|
816 | |
---|
817 | /* Indicate the alignment boundary for an argument of the specified mode and |
---|
818 | type. */ |
---|
819 | #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ |
---|
820 | (((TYPE) != 0) \ |
---|
821 | ? ((TYPE_ALIGN (TYPE) <= PARM_BOUNDARY) \ |
---|
822 | ? PARM_BOUNDARY \ |
---|
823 | : TYPE_ALIGN (TYPE)) \ |
---|
824 | : ((GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY) \ |
---|
825 | ? PARM_BOUNDARY \ |
---|
826 | : GET_MODE_ALIGNMENT (MODE))) |
---|
827 | |
---|
828 | /* Determine where to put an argument to a function. |
---|
829 | Value is zero to push the argument on the stack, |
---|
830 | or a hard register in which to store the argument. |
---|
831 | |
---|
832 | MODE is the argument's machine mode. |
---|
833 | TYPE is the data type of the argument (as a tree). |
---|
834 | This is null for libcalls where that information may |
---|
835 | not be available. |
---|
836 | CUM is a variable of type CUMULATIVE_ARGS which gives info about |
---|
837 | the preceding args and about the function being called. |
---|
838 | NAMED is nonzero if this argument is a named parameter |
---|
839 | (otherwise it is an extra parameter matching an ellipsis). */ |
---|
840 | |
---|
841 | extern struct rtx_def *i960_function_arg (); |
---|
842 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
---|
843 | i960_function_arg(&CUM, MODE, TYPE, NAMED) |
---|
844 | |
---|
845 | /* Define how to find the value returned by a function. |
---|
846 | VALTYPE is the data type of the value (as a tree). |
---|
847 | If the precise function being called is known, FUNC is its FUNCTION_DECL; |
---|
848 | otherwise, FUNC is 0. */ |
---|
849 | |
---|
850 | #define FUNCTION_VALUE(TYPE, FUNC) \ |
---|
851 | gen_rtx (REG, TYPE_MODE (TYPE), 0) |
---|
852 | |
---|
853 | /* Force aggregates and objects larger than 16 bytes to be returned in memory, |
---|
854 | since we only have 4 registers available for return values. */ |
---|
855 | |
---|
856 | #define RETURN_IN_MEMORY(TYPE) \ |
---|
857 | (TYPE_MODE (TYPE) == BLKmode || int_size_in_bytes (TYPE) > 16) |
---|
858 | |
---|
859 | /* Don't default to pcc-struct-return, because we have already specified |
---|
860 | exactly how to return structures in the RETURN_IN_MEMORY macro. */ |
---|
861 | #define DEFAULT_PCC_STRUCT_RETURN 0 |
---|
862 | |
---|
863 | /* For an arg passed partly in registers and partly in memory, |
---|
864 | this is the number of registers used. |
---|
865 | This never happens on 80960. */ |
---|
866 | |
---|
867 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 |
---|
868 | |
---|
869 | /* Output the label for a function definition. |
---|
870 | This handles leaf functions and a few other things for the i960. */ |
---|
871 | |
---|
872 | #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ |
---|
873 | i960_function_name_declare (FILE, NAME, DECL) |
---|
874 | |
---|
875 | /* This macro generates the assembly code for function entry. |
---|
876 | FILE is a stdio stream to output the code to. |
---|
877 | SIZE is an int: how many units of temporary storage to allocate. |
---|
878 | Refer to the array `regs_ever_live' to determine which registers |
---|
879 | to save; `regs_ever_live[I]' is nonzero if register number I |
---|
880 | is ever used in the function. This macro is responsible for |
---|
881 | knowing which registers should not be saved even if used. */ |
---|
882 | |
---|
883 | #define FUNCTION_PROLOGUE(FILE, SIZE) i960_function_prologue ((FILE), (SIZE)) |
---|
884 | |
---|
885 | /* Output assembler code to FILE to increment profiler label # LABELNO |
---|
886 | for profiling a function entry. */ |
---|
887 | |
---|
888 | #define FUNCTION_PROFILER(FILE, LABELNO) \ |
---|
889 | output_function_profiler ((FILE), (LABELNO)); |
---|
890 | |
---|
891 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
---|
892 | the stack pointer does not matter. The value is tested only in |
---|
893 | functions that have frame pointers. |
---|
894 | No definition is equivalent to always zero. */ |
---|
895 | |
---|
896 | #define EXIT_IGNORE_STACK 1 |
---|
897 | |
---|
898 | /* This macro generates the assembly code for function exit, |
---|
899 | on machines that need it. If FUNCTION_EPILOGUE is not defined |
---|
900 | then individual return instructions are generated for each |
---|
901 | return statement. Args are same as for FUNCTION_PROLOGUE. |
---|
902 | |
---|
903 | The function epilogue should not depend on the current stack pointer! |
---|
904 | It should use the frame pointer only. This is mandatory because |
---|
905 | of alloca; we also take advantage of it to omit stack adjustments |
---|
906 | before returning. */ |
---|
907 | |
---|
908 | #define FUNCTION_EPILOGUE(FILE, SIZE) i960_function_epilogue (FILE, SIZE) |
---|
909 | |
---|
910 | /* Addressing modes, and classification of registers for them. */ |
---|
911 | |
---|
912 | /* #define HAVE_POST_INCREMENT */ |
---|
913 | /* #define HAVE_POST_DECREMENT */ |
---|
914 | |
---|
915 | /* #define HAVE_PRE_DECREMENT */ |
---|
916 | /* #define HAVE_PRE_INCREMENT */ |
---|
917 | |
---|
918 | /* Macros to check register numbers against specific register classes. */ |
---|
919 | |
---|
920 | /* These assume that REGNO is a hard or pseudo reg number. |
---|
921 | They give nonzero only if REGNO is a hard reg of the suitable class |
---|
922 | or a pseudo reg currently allocated to a suitable hard reg. |
---|
923 | Since they use reg_renumber, they are safe only once reg_renumber |
---|
924 | has been allocated, which happens in local-alloc.c. */ |
---|
925 | |
---|
926 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
---|
927 | ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) |
---|
928 | #define REGNO_OK_FOR_BASE_P(REGNO) \ |
---|
929 | ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) |
---|
930 | #define REGNO_OK_FOR_FP_P(REGNO) \ |
---|
931 | ((REGNO) < 36 || (unsigned) reg_renumber[REGNO] < 36) |
---|
932 | |
---|
933 | /* Now macros that check whether X is a register and also, |
---|
934 | strictly, whether it is in a specified class. |
---|
935 | |
---|
936 | These macros are specific to the 960, and may be used only |
---|
937 | in code for printing assembler insns and in conditions for |
---|
938 | define_optimization. */ |
---|
939 | |
---|
940 | /* 1 if X is an fp register. */ |
---|
941 | |
---|
942 | #define FP_REG_P(X) (REGNO (X) >= 32 && REGNO (X) < 36) |
---|
943 | |
---|
944 | /* Maximum number of registers that can appear in a valid memory address. */ |
---|
945 | #define MAX_REGS_PER_ADDRESS 2 |
---|
946 | |
---|
947 | #define CONSTANT_ADDRESS_P(X) \ |
---|
948 | (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ |
---|
949 | || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ |
---|
950 | || GET_CODE (X) == HIGH) |
---|
951 | |
---|
952 | /* LEGITIMATE_CONSTANT_P is nonzero if the constant value X |
---|
953 | is a legitimate general operand. |
---|
954 | It is given that X satisfies CONSTANT_P. |
---|
955 | |
---|
956 | Anything but a CONST_DOUBLE can be made to work, excepting 0.0 and 1.0. |
---|
957 | |
---|
958 | ??? This probably should be defined to 1. */ |
---|
959 | |
---|
960 | #define LEGITIMATE_CONSTANT_P(X) \ |
---|
961 | ((GET_CODE (X) != CONST_DOUBLE) || fp_literal ((X), GET_MODE (X))) |
---|
962 | |
---|
963 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
---|
964 | and check its validity for a certain class. |
---|
965 | We have two alternate definitions for each of them. |
---|
966 | The usual definition accepts all pseudo regs; the other rejects |
---|
967 | them unless they have been allocated suitable hard regs. |
---|
968 | The symbol REG_OK_STRICT causes the latter definition to be used. |
---|
969 | |
---|
970 | Most source files want to accept pseudo regs in the hope that |
---|
971 | they will get allocated to the class that the insn wants them to be in. |
---|
972 | Source files for reload pass need to be strict. |
---|
973 | After reload, it makes no difference, since pseudo regs have |
---|
974 | been eliminated by then. */ |
---|
975 | |
---|
976 | #ifndef REG_OK_STRICT |
---|
977 | |
---|
978 | /* Nonzero if X is a hard reg that can be used as an index |
---|
979 | or if it is a pseudo reg. */ |
---|
980 | #define REG_OK_FOR_INDEX_P(X) \ |
---|
981 | (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
---|
982 | /* Nonzero if X is a hard reg that can be used as a base reg |
---|
983 | or if it is a pseudo reg. */ |
---|
984 | #define REG_OK_FOR_BASE_P(X) \ |
---|
985 | (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
---|
986 | |
---|
987 | #define REG_OK_FOR_INDEX_P_STRICT(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) |
---|
988 | #define REG_OK_FOR_BASE_P_STRICT(X) REGNO_OK_FOR_BASE_P (REGNO (X)) |
---|
989 | |
---|
990 | #else |
---|
991 | |
---|
992 | /* Nonzero if X is a hard reg that can be used as an index. */ |
---|
993 | #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) |
---|
994 | /* Nonzero if X is a hard reg that can be used as a base reg. */ |
---|
995 | #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) |
---|
996 | |
---|
997 | #endif |
---|
998 | |
---|
999 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression |
---|
1000 | that is a valid memory address for an instruction. |
---|
1001 | The MODE argument is the machine mode for the MEM expression |
---|
1002 | that wants to use this address. |
---|
1003 | |
---|
1004 | On 80960, legitimate addresses are: |
---|
1005 | base ld (g0),r0 |
---|
1006 | disp (12 or 32 bit) ld foo,r0 |
---|
1007 | base + index ld (g0)[g1*1],r0 |
---|
1008 | base + displ ld 0xf00(g0),r0 |
---|
1009 | base + index*scale + displ ld 0xf00(g0)[g1*4],r0 |
---|
1010 | index*scale + base ld (g0)[g1*4],r0 |
---|
1011 | index*scale + displ ld 0xf00[g1*4],r0 |
---|
1012 | index*scale ld [g1*4],r0 |
---|
1013 | index + base + displ ld 0xf00(g0)[g1*1],r0 |
---|
1014 | |
---|
1015 | In each case, scale can be 1, 2, 4, 8, or 16. */ |
---|
1016 | |
---|
1017 | /* Returns 1 if the scale factor of an index term is valid. */ |
---|
1018 | #define SCALE_TERM_P(X) \ |
---|
1019 | (GET_CODE (X) == CONST_INT \ |
---|
1020 | && (INTVAL (X) == 1 || INTVAL (X) == 2 || INTVAL (X) == 4 \ |
---|
1021 | || INTVAL(X) == 8 || INTVAL (X) == 16)) |
---|
1022 | |
---|
1023 | |
---|
1024 | #ifdef REG_OK_STRICT |
---|
1025 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ |
---|
1026 | { if (legitimate_address_p (MODE, X, 1)) goto ADDR; } |
---|
1027 | #else |
---|
1028 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ |
---|
1029 | { if (legitimate_address_p (MODE, X, 0)) goto ADDR; } |
---|
1030 | #endif |
---|
1031 | |
---|
1032 | /* Try machine-dependent ways of modifying an illegitimate address |
---|
1033 | to be legitimate. If we find one, return the new, valid address. |
---|
1034 | This macro is used in only one place: `memory_address' in explow.c. |
---|
1035 | |
---|
1036 | OLDX is the address as it was before break_out_memory_refs was called. |
---|
1037 | In some cases it is useful to look at this to decide what needs to be done. |
---|
1038 | |
---|
1039 | MODE and WIN are passed so that this macro can use |
---|
1040 | GO_IF_LEGITIMATE_ADDRESS. |
---|
1041 | |
---|
1042 | It is always safe for this macro to do nothing. It exists to recognize |
---|
1043 | opportunities to optimize the output. */ |
---|
1044 | |
---|
1045 | /* On 80960, convert non-canonical addresses to canonical form. */ |
---|
1046 | |
---|
1047 | extern struct rtx_def *legitimize_address (); |
---|
1048 | #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ |
---|
1049 | { rtx orig_x = (X); \ |
---|
1050 | (X) = legitimize_address (X, OLDX, MODE); \ |
---|
1051 | if ((X) != orig_x && memory_address_p (MODE, X)) \ |
---|
1052 | goto WIN; } |
---|
1053 | |
---|
1054 | /* Go to LABEL if ADDR (a legitimate address expression) |
---|
1055 | has an effect that depends on the machine mode it is used for. |
---|
1056 | On the 960 this is never true. */ |
---|
1057 | |
---|
1058 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) |
---|
1059 | |
---|
1060 | /* Specify the machine mode that this machine uses |
---|
1061 | for the index in the tablejump instruction. */ |
---|
1062 | #define CASE_VECTOR_MODE SImode |
---|
1063 | |
---|
1064 | /* Define this if the tablejump instruction expects the table |
---|
1065 | to contain offsets from the address of the table. |
---|
1066 | Do not define this if the table should contain absolute addresses. */ |
---|
1067 | /* #define CASE_VECTOR_PC_RELATIVE */ |
---|
1068 | |
---|
1069 | /* Specify the tree operation to be used to convert reals to integers. */ |
---|
1070 | #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR |
---|
1071 | |
---|
1072 | /* This is the kind of divide that is easiest to do in the general case. */ |
---|
1073 | #define EASY_DIV_EXPR TRUNC_DIV_EXPR |
---|
1074 | |
---|
1075 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
---|
1076 | #define DEFAULT_SIGNED_CHAR 0 |
---|
1077 | |
---|
1078 | /* Allow and ignore #sccs directives. */ |
---|
1079 | #define SCCS_DIRECTIVE |
---|
1080 | |
---|
1081 | /* Max number of bytes we can move from memory to memory |
---|
1082 | in one reasonably fast instruction. */ |
---|
1083 | #define MOVE_MAX 16 |
---|
1084 | |
---|
1085 | /* Define if operations between registers always perform the operation |
---|
1086 | on the full register even if a narrower mode is specified. */ |
---|
1087 | #define WORD_REGISTER_OPERATIONS |
---|
1088 | |
---|
1089 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD |
---|
1090 | will either zero-extend or sign-extend. The value of this macro should |
---|
1091 | be the code that says which one of the two operations is implicitly |
---|
1092 | done, NIL if none. */ |
---|
1093 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND |
---|
1094 | |
---|
1095 | /* Nonzero if access to memory by bytes is no faster than for words. |
---|
1096 | Defining this results in worse code on the i960. */ |
---|
1097 | |
---|
1098 | #define SLOW_BYTE_ACCESS 0 |
---|
1099 | |
---|
1100 | /* We assume that the store-condition-codes instructions store 0 for false |
---|
1101 | and some other value for true. This is the value stored for true. */ |
---|
1102 | |
---|
1103 | #define STORE_FLAG_VALUE 1 |
---|
1104 | |
---|
1105 | /* Define this to be nonzero if shift instructions ignore all but the low-order |
---|
1106 | few bits. */ |
---|
1107 | #define SHIFT_COUNT_TRUNCATED 1 |
---|
1108 | |
---|
1109 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits |
---|
1110 | is done just by pretending it is already truncated. */ |
---|
1111 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 |
---|
1112 | |
---|
1113 | /* Specify the machine mode that pointers have. |
---|
1114 | After generation of rtl, the compiler makes no further distinction |
---|
1115 | between pointers and any other objects of this machine mode. */ |
---|
1116 | #define Pmode SImode |
---|
1117 | |
---|
1118 | /* Specify the widest mode that BLKmode objects can be promoted to */ |
---|
1119 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) |
---|
1120 | |
---|
1121 | /* These global variables are used to pass information between |
---|
1122 | cc setter and cc user at insn emit time. */ |
---|
1123 | |
---|
1124 | extern struct rtx_def *i960_compare_op0, *i960_compare_op1; |
---|
1125 | |
---|
1126 | /* Define the function that build the compare insn for scc and bcc. */ |
---|
1127 | |
---|
1128 | extern struct rtx_def *gen_compare_reg (); |
---|
1129 | |
---|
1130 | /* Add any extra modes needed to represent the condition code. |
---|
1131 | |
---|
1132 | Also, signed and unsigned comparisons are distinguished, as |
---|
1133 | are operations which are compatible with chkbit insns. */ |
---|
1134 | #define EXTRA_CC_MODES CC_UNSmode, CC_CHKmode |
---|
1135 | |
---|
1136 | /* Define the names for the modes specified above. */ |
---|
1137 | #define EXTRA_CC_NAMES "CC_UNS", "CC_CHK" |
---|
1138 | |
---|
1139 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
---|
1140 | return the mode to be used for the comparison. For floating-point, CCFPmode |
---|
1141 | should be used. CC_NOOVmode should be used when the first operand is a |
---|
1142 | PLUS, MINUS, or NEG. CCmode should be used when no special processing is |
---|
1143 | needed. */ |
---|
1144 | #define SELECT_CC_MODE(OP,X,Y) select_cc_mode (OP, X) |
---|
1145 | |
---|
1146 | /* A function address in a call instruction is a byte address |
---|
1147 | (for indexing purposes) so give the MEM rtx a byte's mode. */ |
---|
1148 | #define FUNCTION_MODE SImode |
---|
1149 | |
---|
1150 | /* Define this if addresses of constant functions |
---|
1151 | shouldn't be put through pseudo regs where they can be cse'd. |
---|
1152 | Desirable on machines where ordinary constants are expensive |
---|
1153 | but a CALL with constant address is cheap. */ |
---|
1154 | #define NO_FUNCTION_CSE |
---|
1155 | |
---|
1156 | /* Use memcpy, etc. instead of bcopy. */ |
---|
1157 | |
---|
1158 | #ifndef WIND_RIVER |
---|
1159 | #define TARGET_MEM_FUNCTIONS 1 |
---|
1160 | #endif |
---|
1161 | |
---|
1162 | /* Compute the cost of computing a constant rtl expression RTX |
---|
1163 | whose rtx-code is CODE. The body of this macro is a portion |
---|
1164 | of a switch statement. If the code is computed here, |
---|
1165 | return it with a return statement. Otherwise, break from the switch. */ |
---|
1166 | |
---|
1167 | /* Constants that can be (non-ldconst) insn operands are cost 0. Constants |
---|
1168 | that can be non-ldconst operands in rare cases are cost 1. Other constants |
---|
1169 | have higher costs. */ |
---|
1170 | |
---|
1171 | #define CONST_COSTS(RTX, CODE, OUTER_CODE) \ |
---|
1172 | case CONST_INT: \ |
---|
1173 | if ((INTVAL (RTX) >= 0 && INTVAL (RTX) < 32) \ |
---|
1174 | || power2_operand (RTX, VOIDmode)) \ |
---|
1175 | return 0; \ |
---|
1176 | else if (INTVAL (RTX) >= -31 && INTVAL (RTX) < 0) \ |
---|
1177 | return 1; \ |
---|
1178 | case CONST: \ |
---|
1179 | case LABEL_REF: \ |
---|
1180 | case SYMBOL_REF: \ |
---|
1181 | return (TARGET_FLAG_C_SERIES ? 6 : 8); \ |
---|
1182 | case CONST_DOUBLE: \ |
---|
1183 | if ((RTX) == CONST0_RTX (DFmode) || (RTX) == CONST0_RTX (SFmode) \ |
---|
1184 | || (RTX) == CONST1_RTX (DFmode) || (RTX) == CONST1_RTX (SFmode))\ |
---|
1185 | return 1; \ |
---|
1186 | return 12; |
---|
1187 | |
---|
1188 | /* The i960 offers addressing modes which are "as cheap as a register". |
---|
1189 | See i960.c (or gcc.texinfo) for details. */ |
---|
1190 | |
---|
1191 | #define ADDRESS_COST(RTX) \ |
---|
1192 | (GET_CODE (RTX) == REG ? 1 : i960_address_cost (RTX)) |
---|
1193 | |
---|
1194 | /* Control the assembler format that we output. */ |
---|
1195 | |
---|
1196 | /* Output at beginning of assembler file. */ |
---|
1197 | |
---|
1198 | #define ASM_FILE_START(file) |
---|
1199 | |
---|
1200 | /* Output to assembler file text saying following lines |
---|
1201 | may contain character constants, extra white space, comments, etc. */ |
---|
1202 | |
---|
1203 | #define ASM_APP_ON "" |
---|
1204 | |
---|
1205 | /* Output to assembler file text saying following lines |
---|
1206 | no longer contain unusual constructs. */ |
---|
1207 | |
---|
1208 | #define ASM_APP_OFF "" |
---|
1209 | |
---|
1210 | /* Output before read-only data. */ |
---|
1211 | |
---|
1212 | #define TEXT_SECTION_ASM_OP ".text" |
---|
1213 | |
---|
1214 | /* Output before writable data. */ |
---|
1215 | |
---|
1216 | #define DATA_SECTION_ASM_OP ".data" |
---|
1217 | |
---|
1218 | /* How to refer to registers in assembler output. |
---|
1219 | This sequence is indexed by compiler's hard-register-number (see above). */ |
---|
1220 | |
---|
1221 | #define REGISTER_NAMES { \ |
---|
1222 | "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", \ |
---|
1223 | "g8", "g9", "g10", "g11", "g12", "g13", "g14", "fp", \ |
---|
1224 | "pfp","sp", "rip", "r3", "r4", "r5", "r6", "r7", \ |
---|
1225 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ |
---|
1226 | "fp0","fp1","fp2", "fp3", "cc", "fake" } |
---|
1227 | |
---|
1228 | /* How to renumber registers for dbx and gdb. |
---|
1229 | In the 960 encoding, g0..g15 are registers 16..31. */ |
---|
1230 | |
---|
1231 | #define DBX_REGISTER_NUMBER(REGNO) \ |
---|
1232 | (((REGNO) < 16) ? (REGNO) + 16 \ |
---|
1233 | : (((REGNO) > 31) ? (REGNO) : (REGNO) - 16)) |
---|
1234 | |
---|
1235 | /* Don't emit dbx records longer than this. This is an arbitrary value. */ |
---|
1236 | #define DBX_CONTIN_LENGTH 1500 |
---|
1237 | |
---|
1238 | /* This is how to output a note to DBX telling it the line number |
---|
1239 | to which the following sequence of instructions corresponds. */ |
---|
1240 | |
---|
1241 | #define ASM_OUTPUT_SOURCE_LINE(FILE, LINE) \ |
---|
1242 | { if (write_symbols == SDB_DEBUG) { \ |
---|
1243 | fprintf ((FILE), "\t.ln %d\n", \ |
---|
1244 | (sdb_begin_function_line \ |
---|
1245 | ? (LINE) - sdb_begin_function_line : 1)); \ |
---|
1246 | } else if (write_symbols == DBX_DEBUG) { \ |
---|
1247 | fprintf((FILE),"\t.stabd 68,0,%d\n",(LINE)); \ |
---|
1248 | } } |
---|
1249 | |
---|
1250 | /* This is how to output the definition of a user-level label named NAME, |
---|
1251 | such as the label on a static function or variable NAME. */ |
---|
1252 | |
---|
1253 | #define ASM_OUTPUT_LABEL(FILE,NAME) \ |
---|
1254 | do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) |
---|
1255 | |
---|
1256 | /* This is how to output a command to make the user-level label named NAME |
---|
1257 | defined for reference from other files. */ |
---|
1258 | |
---|
1259 | #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ |
---|
1260 | { fputs ("\t.globl ", FILE); \ |
---|
1261 | assemble_name (FILE, NAME); \ |
---|
1262 | fputs ("\n", FILE); } |
---|
1263 | |
---|
1264 | /* This is how to output a reference to a user-level label named NAME. |
---|
1265 | `assemble_name' uses this. */ |
---|
1266 | |
---|
1267 | #define ASM_OUTPUT_LABELREF(FILE,NAME) fprintf (FILE, "_%s", NAME) |
---|
1268 | |
---|
1269 | /* This is how to output an internal numbered label where |
---|
1270 | PREFIX is the class of label and NUM is the number within the class. */ |
---|
1271 | |
---|
1272 | #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ |
---|
1273 | fprintf (FILE, "%s%d:\n", PREFIX, NUM) |
---|
1274 | |
---|
1275 | /* This is how to store into the string LABEL |
---|
1276 | the symbol_ref name of an internal numbered label where |
---|
1277 | PREFIX is the class of label and NUM is the number within the class. |
---|
1278 | This is suitable for output with `assemble_name'. */ |
---|
1279 | |
---|
1280 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ |
---|
1281 | sprintf (LABEL, "*%s%d", PREFIX, NUM) |
---|
1282 | |
---|
1283 | /* This is how to output an assembler line defining a `long double' |
---|
1284 | constant. */ |
---|
1285 | |
---|
1286 | #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) i960_output_long_double(FILE, VALUE) |
---|
1287 | |
---|
1288 | /* This is how to output an assembler line defining a `double' constant. */ |
---|
1289 | |
---|
1290 | #define ASM_OUTPUT_DOUBLE(FILE,VALUE) i960_output_double(FILE, VALUE) |
---|
1291 | |
---|
1292 | /* This is how to output an assembler line defining a `float' constant. */ |
---|
1293 | |
---|
1294 | #define ASM_OUTPUT_FLOAT(FILE,VALUE) i960_output_float(FILE, VALUE) |
---|
1295 | |
---|
1296 | /* This is how to output an assembler line defining an `int' constant. */ |
---|
1297 | |
---|
1298 | #define ASM_OUTPUT_INT(FILE,VALUE) \ |
---|
1299 | ( fprintf (FILE, "\t.word "), \ |
---|
1300 | output_addr_const (FILE, (VALUE)), \ |
---|
1301 | fprintf (FILE, "\n")) |
---|
1302 | |
---|
1303 | /* Likewise for `char' and `short' constants. */ |
---|
1304 | |
---|
1305 | #define ASM_OUTPUT_SHORT(FILE,VALUE) \ |
---|
1306 | ( fprintf (FILE, "\t.short "), \ |
---|
1307 | output_addr_const (FILE, (VALUE)), \ |
---|
1308 | fprintf (FILE, "\n")) |
---|
1309 | |
---|
1310 | #define ASM_OUTPUT_CHAR(FILE,VALUE) \ |
---|
1311 | ( fprintf (FILE, "\t.byte "), \ |
---|
1312 | output_addr_const (FILE, (VALUE)), \ |
---|
1313 | fprintf (FILE, "\n")) |
---|
1314 | |
---|
1315 | /* This is how to output an assembler line for a numeric constant byte. */ |
---|
1316 | |
---|
1317 | #define ASM_OUTPUT_BYTE(FILE,VALUE) \ |
---|
1318 | fprintf (FILE, "\t.byte 0x%x\n", (VALUE)) |
---|
1319 | |
---|
1320 | #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ |
---|
1321 | fprintf (FILE, "\tst\t%s,(sp)\n\taddo\t4,sp,sp\n", reg_names[REGNO]) |
---|
1322 | |
---|
1323 | /* This is how to output an insn to pop a register from the stack. |
---|
1324 | It need not be very fast code. */ |
---|
1325 | |
---|
1326 | #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ |
---|
1327 | fprintf (FILE, "\tsubo\t4,sp,sp\n\tld\t(sp),%s\n", reg_names[REGNO]) |
---|
1328 | |
---|
1329 | /* This is how to output an element of a case-vector that is absolute. */ |
---|
1330 | |
---|
1331 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ |
---|
1332 | fprintf (FILE, "\t.word L%d\n", VALUE) |
---|
1333 | |
---|
1334 | /* This is how to output an element of a case-vector that is relative. */ |
---|
1335 | |
---|
1336 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ |
---|
1337 | fprintf (FILE, "\t.word L%d-L%d\n", VALUE, REL) |
---|
1338 | |
---|
1339 | /* This is how to output an assembler line that says to advance the |
---|
1340 | location counter to a multiple of 2**LOG bytes. */ |
---|
1341 | |
---|
1342 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ |
---|
1343 | fprintf (FILE, "\t.align %d\n", (LOG)) |
---|
1344 | |
---|
1345 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ |
---|
1346 | fprintf (FILE, "\t.space %d\n", (SIZE)) |
---|
1347 | |
---|
1348 | /* This says how to output an assembler line |
---|
1349 | to define a global common symbol. */ |
---|
1350 | |
---|
1351 | /* For common objects, output unpadded size... gld960 & lnk960 both |
---|
1352 | have code to align each common object at link time. Also, if size |
---|
1353 | is 0, treat this as a declaration, not a definition - i.e., |
---|
1354 | do nothing at all. */ |
---|
1355 | |
---|
1356 | #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ |
---|
1357 | { if ((SIZE) != 0) \ |
---|
1358 | { \ |
---|
1359 | fputs (".globl ", (FILE)), \ |
---|
1360 | assemble_name ((FILE), (NAME)), \ |
---|
1361 | fputs ("\n.comm ", (FILE)), \ |
---|
1362 | assemble_name ((FILE), (NAME)), \ |
---|
1363 | fprintf ((FILE), ",%d\n", (SIZE)); \ |
---|
1364 | } \ |
---|
1365 | } |
---|
1366 | |
---|
1367 | /* This says how to output an assembler line to define a local common symbol. |
---|
1368 | Output unpadded size, with request to linker to align as requested. |
---|
1369 | 0 size should not be possible here. */ |
---|
1370 | |
---|
1371 | #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \ |
---|
1372 | ( fputs (".bss\t", (FILE)), \ |
---|
1373 | assemble_name ((FILE), (NAME)), \ |
---|
1374 | fprintf ((FILE), ",%d,%d\n", (SIZE), \ |
---|
1375 | ((ALIGN) <= 8 ? 0 \ |
---|
1376 | : ((ALIGN) <= 16 ? 1 \ |
---|
1377 | : ((ALIGN) <= 32 ? 2 \ |
---|
1378 | : ((ALIGN <= 64 ? 3 : 4))))))) |
---|
1379 | |
---|
1380 | /* Output text for an #ident directive. */ |
---|
1381 | #define ASM_OUTPUT_IDENT(FILE, STR) fprintf(FILE, "\t# %s\n", STR); |
---|
1382 | |
---|
1383 | /* Align code to 8 byte boundary if TARGET_CODE_ALIGN is true. */ |
---|
1384 | |
---|
1385 | #define ASM_OUTPUT_ALIGN_CODE(FILE) \ |
---|
1386 | { if (TARGET_CODE_ALIGN) fputs("\t.align 3\n",FILE); } |
---|
1387 | |
---|
1388 | /* Store in OUTPUT a string (made with alloca) containing |
---|
1389 | an assembler-name for a local static variable named NAME. |
---|
1390 | LABELNO is an integer which is different for each call. */ |
---|
1391 | |
---|
1392 | #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ |
---|
1393 | ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ |
---|
1394 | sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) |
---|
1395 | |
---|
1396 | /* Define the parentheses used to group arithmetic operations |
---|
1397 | in assembler code. */ |
---|
1398 | |
---|
1399 | #define ASM_OPEN_PAREN "(" |
---|
1400 | #define ASM_CLOSE_PAREN ")" |
---|
1401 | |
---|
1402 | /* Define results of standard character escape sequences. */ |
---|
1403 | #define TARGET_BELL 007 |
---|
1404 | #define TARGET_BS 010 |
---|
1405 | #define TARGET_TAB 011 |
---|
1406 | #define TARGET_NEWLINE 012 |
---|
1407 | #define TARGET_VT 013 |
---|
1408 | #define TARGET_FF 014 |
---|
1409 | #define TARGET_CR 015 |
---|
1410 | |
---|
1411 | /* Output assembler code to FILE to initialize this source file's |
---|
1412 | basic block profiling info, if that has not already been done. */ |
---|
1413 | |
---|
1414 | #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \ |
---|
1415 | { fprintf (FILE, "\tld LPBX0,g12\n"); \ |
---|
1416 | fprintf (FILE, "\tcmpobne 0,g12,LPY%d\n",LABELNO);\ |
---|
1417 | fprintf (FILE, "\tlda LPBX0,g12\n"); \ |
---|
1418 | fprintf (FILE, "\tcall ___bb_init_func\n"); \ |
---|
1419 | fprintf (FILE, "LPY%d:\n",LABELNO); } |
---|
1420 | |
---|
1421 | /* Output assembler code to FILE to increment the entry-count for |
---|
1422 | the BLOCKNO'th basic block in this source file. */ |
---|
1423 | |
---|
1424 | #define BLOCK_PROFILER(FILE, BLOCKNO) \ |
---|
1425 | { int blockn = (BLOCKNO); \ |
---|
1426 | fprintf (FILE, "\tld LPBX2+%d,g12\n", 4 * blockn); \ |
---|
1427 | fprintf (FILE, "\taddo g12,1,g12\n"); \ |
---|
1428 | fprintf (FILE, "\tst g12,LPBX2+%d\n", 4 * blockn); } |
---|
1429 | |
---|
1430 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
---|
1431 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. |
---|
1432 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ |
---|
1433 | |
---|
1434 | #define PRINT_OPERAND(FILE, X, CODE) \ |
---|
1435 | i960_print_operand (FILE, X, CODE); |
---|
1436 | |
---|
1437 | /* Print a memory address as an operand to reference that memory location. */ |
---|
1438 | |
---|
1439 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ |
---|
1440 | i960_print_operand_addr (FILE, ADDR) |
---|
1441 | |
---|
1442 | /* Output assembler code for a block containing the constant parts |
---|
1443 | of a trampoline, leaving space for the variable parts. */ |
---|
1444 | |
---|
1445 | /* On the i960, the trampoline contains three instructions: |
---|
1446 | ldconst _function, r4 |
---|
1447 | ldconst static addr, r3 |
---|
1448 | jump (r4) */ |
---|
1449 | |
---|
1450 | #define TRAMPOLINE_TEMPLATE(FILE) \ |
---|
1451 | { \ |
---|
1452 | ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x8C203000)); \ |
---|
1453 | ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ |
---|
1454 | ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x8C183000)); \ |
---|
1455 | ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ |
---|
1456 | ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x84212000)); \ |
---|
1457 | } |
---|
1458 | |
---|
1459 | /* Length in units of the trampoline for entering a nested function. */ |
---|
1460 | |
---|
1461 | #define TRAMPOLINE_SIZE 20 |
---|
1462 | |
---|
1463 | /* Emit RTL insns to initialize the variable parts of a trampoline. |
---|
1464 | FNADDR is an RTX for the address of the function's pure code. |
---|
1465 | CXT is an RTX for the static chain value for the function. */ |
---|
1466 | |
---|
1467 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ |
---|
1468 | { \ |
---|
1469 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), \ |
---|
1470 | FNADDR); \ |
---|
1471 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 12)), \ |
---|
1472 | CXT); \ |
---|
1473 | } |
---|
1474 | |
---|
1475 | #if 0 |
---|
1476 | /* Promote char and short arguments to ints, when want compatibility with |
---|
1477 | the iC960 compilers. */ |
---|
1478 | |
---|
1479 | /* ??? In order for this to work, all users would need to be changed |
---|
1480 | to test the value of the macro at run time. */ |
---|
1481 | #define PROMOTE_PROTOTYPES TARGET_CLEAN_LINKAGE |
---|
1482 | /* ??? This does not exist. */ |
---|
1483 | #define PROMOTE_RETURN TARGET_CLEAN_LINKAGE |
---|
1484 | #endif |
---|
1485 | |
---|
1486 | /* Instruction type definitions. Used to alternate instructions types for |
---|
1487 | better performance on the C series chips. */ |
---|
1488 | |
---|
1489 | enum insn_types { I_TYPE_REG, I_TYPE_MEM, I_TYPE_CTRL }; |
---|
1490 | |
---|
1491 | /* Holds the insn type of the last insn output to the assembly file. */ |
---|
1492 | |
---|
1493 | extern enum insn_types i960_last_insn_type; |
---|
1494 | |
---|
1495 | /* Parse opcodes, and set the insn last insn type based on them. */ |
---|
1496 | |
---|
1497 | #define ASM_OUTPUT_OPCODE(FILE, INSN) i960_scan_opcode (INSN) |
---|
1498 | |
---|
1499 | /* Table listing what rtl codes each predicate in i960.c will accept. */ |
---|
1500 | |
---|
1501 | #define PREDICATE_CODES \ |
---|
1502 | {"fpmove_src_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ |
---|
1503 | LABEL_REF, SUBREG, REG, MEM}}, \ |
---|
1504 | {"arith_operand", {SUBREG, REG, CONST_INT}}, \ |
---|
1505 | {"fp_arith_operand", {SUBREG, REG, CONST_DOUBLE}}, \ |
---|
1506 | {"signed_arith_operand", {SUBREG, REG, CONST_INT}}, \ |
---|
1507 | {"literal", {CONST_INT}}, \ |
---|
1508 | {"fp_literal_one", {CONST_DOUBLE}}, \ |
---|
1509 | {"fp_literal_double", {CONST_DOUBLE}}, \ |
---|
1510 | {"fp_literal", {CONST_DOUBLE}}, \ |
---|
1511 | {"signed_literal", {CONST_INT}}, \ |
---|
1512 | {"symbolic_memory_operand", {SUBREG, MEM}}, \ |
---|
1513 | {"eq_or_neq", {EQ, NE}}, \ |
---|
1514 | {"arith32_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST_INT, \ |
---|
1515 | CONST_DOUBLE, CONST}}, \ |
---|
1516 | {"power2_operand", {CONST_INT}}, \ |
---|
1517 | {"cmplpower2_operand", {CONST_INT}}, |
---|
1518 | |
---|
1519 | /* Define functions in i960.c and used in insn-output.c. */ |
---|
1520 | |
---|
1521 | extern char *i960_output_ldconst (); |
---|
1522 | extern char *i960_output_call_insn (); |
---|
1523 | extern char *i960_output_ret_insn (); |
---|
1524 | |
---|
1525 | /* Defined in reload.c, and used in insn-recog.c. */ |
---|
1526 | |
---|
1527 | extern int rtx_equal_function_value_matters; |
---|