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Revision 8834, 71.7 KB checked in by ghudson, 28 years ago (diff)
This commit was generated by cvs2svn to compensate for changes in r8833, which included commits to RCS files with non-trunk default branches.

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1	;;- Machine description for GNU compiler, ns32000 Version
2	;; Copyright (C) 1988, 1994 Free Software Foundation, Inc.
3	;; Contributed by Michael Tiemann (tiemann@cygnus.com)
4
5	;; This file is part of GNU CC.
6
7	;; GNU CC is free software; you can redistribute it and/or modify
8	;; it under the terms of the GNU General Public License as published by
9	;; the Free Software Foundation; either version 2, or (at your option)
10	;; any later version.
11
12	;; GNU CC is distributed in the hope that it will be useful,
13	;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14	;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15	;; GNU General Public License for more details.
16
17	;; You should have received a copy of the GNU General Public License
18	;; along with GNU CC; see the file COPYING. If not, write to
19	;; the Free Software Foundation, 59 Temple Place - Suite 330,
20	;; Boston, MA 02111-1307, USA.
21
22
23	; BUGS:
24	;; Insert no-op between an insn with memory read-write operands
25	;; following by a scale-indexing operation.
26	;; The Sequent assembler does not allow addresses to be used
27	;; except in insns which explicitly compute an effective address.
28	;; I.e., one cannot say "cmpd _p,@_x"
29	;; Implement unsigned multiplication??
30
31	;;- Instruction patterns. When multiple patterns apply,
32	;;- the first one in the file is chosen.
33	;;-
34	;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
35	;;-
36	;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
37	;;- updates for most instructions.
38
39	;; We don't want to allow a constant operand for test insns because
40	;; (set (cc0) (const_int foo)) has no mode information. Such insns will
41	;; be folded while optimizing anyway.
42
43	(define_insn "tstsi"
44	[(set (cc0)
45	(match_operand:SI 0 "nonimmediate_operand" "rm"))]
46	""
47	"*
48	{ cc_status.flags \|= CC_REVERSED;
49	operands[1] = const0_rtx;
50	return \"cmpqd %1,%0\"; }")
51
52	(define_insn "tsthi"
53	[(set (cc0)
54	(match_operand:HI 0 "nonimmediate_operand" "g"))]
55	""
56	"*
57	{ cc_status.flags \|= CC_REVERSED;
58	operands[1] = const0_rtx;
59	return \"cmpqw %1,%0\"; }")
60
61	(define_insn "tstqi"
62	[(set (cc0)
63	(match_operand:QI 0 "nonimmediate_operand" "g"))]
64	""
65	"*
66	{ cc_status.flags \|= CC_REVERSED;
67	operands[1] = const0_rtx;
68	return \"cmpqb %1,%0\"; }")
69
70	(define_insn "tstdf"
71	[(set (cc0)
72	(match_operand:DF 0 "general_operand" "fmF"))]
73	"TARGET_32081"
74	"*
75	{ cc_status.flags \|= CC_REVERSED;
76	operands[1] = CONST0_RTX (DFmode);
77	return \"cmpl %1,%0\"; }")
78
79	(define_insn "tstsf"
80	[(set (cc0)
81	(match_operand:SF 0 "general_operand" "fmF"))]
82	"TARGET_32081"
83	"*
84	{ cc_status.flags \|= CC_REVERSED;
85	operands[1] = CONST0_RTX (SFmode);
86	return \"cmpf %1,%0\"; }")
87
88	(define_insn "cmpsi"
89	[(set (cc0)
90	(compare (match_operand:SI 0 "nonimmediate_operand" "rmn")
91	(match_operand:SI 1 "general_operand" "rmn")))]
92	""
93	"*
94	{
95	if (GET_CODE (operands[1]) == CONST_INT)
96	{
97	int i = INTVAL (operands[1]);
98	if (i <= 7 && i >= -8)
99	{
100	cc_status.flags \|= CC_REVERSED;
101	return \"cmpqd %1,%0\";
102	}
103	}
104	cc_status.flags &= ~CC_REVERSED;
105	if (GET_CODE (operands[0]) == CONST_INT)
106	{
107	int i = INTVAL (operands[0]);
108	if (i <= 7 && i >= -8)
109	return \"cmpqd %0,%1\";
110	}
111	return \"cmpd %0,%1\";
112	}")
113
114	(define_insn "cmphi"
115	[(set (cc0)
116	(compare (match_operand:HI 0 "nonimmediate_operand" "g")
117	(match_operand:HI 1 "general_operand" "g")))]
118	""
119	"*
120	{
121	if (GET_CODE (operands[1]) == CONST_INT)
122	{
123	short i = INTVAL (operands[1]);
124	if (i <= 7 && i >= -8)
125	{
126	cc_status.flags \|= CC_REVERSED;
127	if (INTVAL (operands[1]) > 7)
128	operands[1] = gen_rtx(CONST_INT, VOIDmode, i);
129	return \"cmpqw %1,%0\";
130	}
131	}
132	cc_status.flags &= ~CC_REVERSED;
133	if (GET_CODE (operands[0]) == CONST_INT)
134	{
135	short i = INTVAL (operands[0]);
136	if (i <= 7 && i >= -8)
137	{
138	if (INTVAL (operands[0]) > 7)
139	operands[0] = gen_rtx(CONST_INT, VOIDmode, i);
140	return \"cmpqw %0,%1\";
141	}
142	}
143	return \"cmpw %0,%1\";
144	}")
145
146	(define_insn "cmpqi"
147	[(set (cc0)
148	(compare (match_operand:QI 0 "nonimmediate_operand" "g")
149	(match_operand:QI 1 "general_operand" "g")))]
150	""
151	"*
152	{
153	if (GET_CODE (operands[1]) == CONST_INT)
154	{
155	char i = INTVAL (operands[1]);
156	if (i <= 7 && i >= -8)
157	{
158	cc_status.flags \|= CC_REVERSED;
159	if (INTVAL (operands[1]) > 7)
160	operands[1] = gen_rtx(CONST_INT, VOIDmode, i);
161	return \"cmpqb %1,%0\";
162	}
163	}
164	cc_status.flags &= ~CC_REVERSED;
165	if (GET_CODE (operands[0]) == CONST_INT)
166	{
167	char i = INTVAL (operands[0]);
168	if (i <= 7 && i >= -8)
169	{
170	if (INTVAL (operands[0]) > 7)
171	operands[0] = gen_rtx(CONST_INT, VOIDmode, i);
172	return \"cmpqb %0,%1\";
173	}
174	}
175	return \"cmpb %0,%1\";
176	}")
177
178	(define_insn "cmpdf"
179	[(set (cc0)
180	(compare (match_operand:DF 0 "general_operand" "fmF")
181	(match_operand:DF 1 "general_operand" "fmF")))]
182	"TARGET_32081"
183	"cmpl %0,%1")
184
185	(define_insn "cmpsf"
186	[(set (cc0)
187	(compare (match_operand:SF 0 "general_operand" "fmF")
188	(match_operand:SF 1 "general_operand" "fmF")))]
189	"TARGET_32081"
190	"cmpf %0,%1")
191
192	(define_insn "movdf"
193	[(set (match_operand:DF 0 "general_operand" "=fg<")
194	(match_operand:DF 1 "general_operand" "fFg"))]
195	""
196	"*
197	{
198	if (FP_REG_P (operands[0]))
199	{
200	if (FP_REG_P (operands[1]) \|\| GET_CODE (operands[1]) == CONST_DOUBLE)
201	return \"movl %1,%0\";
202	if (REG_P (operands[1]))
203	{
204	rtx xoperands[2];
205	xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
206	output_asm_insn (\"movd %1,tos\", xoperands);
207	output_asm_insn (\"movd %1,tos\", operands);
208	return \"movl tos,%0\";
209	}
210	return \"movl %1,%0\";
211	}
212	else if (FP_REG_P (operands[1]))
213	{
214	if (REG_P (operands[0]))
215	{
216	output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands);
217	operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
218	return \"movd tos,%0\";
219	}
220	else
221	return \"movl %1,%0\";
222	}
223	return output_move_double (operands);
224	}")
225
226	(define_insn "movsf"
227	[(set (match_operand:SF 0 "general_operand" "=fg<")
228	(match_operand:SF 1 "general_operand" "fFg"))]
229	""
230	"*
231	{
232	if (FP_REG_P (operands[0]))
233	{
234	if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
235	return \"movd %1,tos\;movf tos,%0\";
236	else
237	return \"movf %1,%0\";
238	}
239	else if (FP_REG_P (operands[1]))
240	{
241	if (REG_P (operands[0]))
242	return \"movf %1,tos\;movd tos,%0\";
243	return \"movf %1,%0\";
244	}
245	#if 0 /* Someone suggested this for the Sequent. Is it needed? */
246	else if (GET_CODE (operands[1]) == CONST_DOUBLE)
247	return \"movf %1,%0\";
248	#endif
249	/* There was a #if 0 around this, but that was erroneous
250	for many machines -- rms. */
251	#ifndef MOVD_FLOAT_OK
252	/* GAS understands floating constants in ordinary movd instructions
253	but other assemblers might object. */
254	else if (GET_CODE (operands[1]) == CONST_DOUBLE)
255	{
256	union {int i[2]; float f; double d;} convrt;
257	convrt.i[0] = CONST_DOUBLE_LOW (operands[1]);
258	convrt.i[1] = CONST_DOUBLE_HIGH (operands[1]);
259	convrt.f = convrt.d;
260
261	/* Is there a better machine-independent way to to this? */
262	operands[1] = gen_rtx (CONST_INT, VOIDmode, convrt.i[0]);
263	return \"movd %1,%0\";
264	}
265	#endif
266	else return \"movd %1,%0\";
267	}")
268
269	(define_insn ""
270	[(set (match_operand:TI 0 "memory_operand" "=m")
271	(match_operand:TI 1 "memory_operand" "m"))]
272	""
273	"movmd %1,%0,4")
274
275	(define_insn "movdi"
276	[(set (match_operand:DI 0 "general_operand" "=g<,*f,g")
277	(match_operand:DI 1 "general_operand" "gF,g,*f"))]
278	""
279	"*
280	{
281	if (FP_REG_P (operands[0]))
282	{
283	if (FP_REG_P (operands[1]) \|\| GET_CODE (operands[1]) == CONST_DOUBLE)
284	return \"movl %1,%0\";
285	if (REG_P (operands[1]))
286	{
287	rtx xoperands[2];
288	xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
289	output_asm_insn (\"movd %1,tos\", xoperands);
290	output_asm_insn (\"movd %1,tos\", operands);
291	return \"movl tos,%0\";
292	}
293	return \"movl %1,%0\";
294	}
295	else if (FP_REG_P (operands[1]))
296	{
297	if (REG_P (operands[0]))
298	{
299	output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands);
300	operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
301	return \"movd tos,%0\";
302	}
303	else
304	return \"movl %1,%0\";
305	}
306	return output_move_double (operands);
307	}")
308
309	;; This special case must precede movsi.
310	(define_insn ""
311	[(set (reg:SI 17)
312	(match_operand:SI 0 "general_operand" "rmn"))]
313	""
314	"lprd sp,%0")
315
316	(define_insn "movsi"
317	[(set (match_operand:SI 0 "general_operand" "=g<,g<,*f,g,x")
318	(match_operand:SI 1 "general_operand" "g,?xy,g,*f,rmn"))]
319	""
320	"*
321	{
322	extern int flag_pic; \
323
324	if (FP_REG_P (operands[0]))
325	{
326	if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
327	return \"movd %1,tos\;movf tos,%0\";
328	else
329	return \"movf %1,%0\";
330	}
331	else if (FP_REG_P (operands[1]))
332	{
333	if (REG_P (operands[0]))
334	return \"movf %1,tos\;movd tos,%0\";
335	return \"movf %1,%0\";
336	}
337	if (GET_CODE (operands[0]) == REG
338	&& REGNO (operands[0]) == FRAME_POINTER_REGNUM)
339	return \"lprd fp,%1\";
340	if (GET_CODE (operands[1]) == CONST_DOUBLE)
341	operands[1]
342	= gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_LOW (operands[1]));
343	if (GET_CODE (operands[1]) == CONST_INT)
344	{
345	int i = INTVAL (operands[1]);
346	if (! TARGET_32532)
347	{
348	if (i <= 7 && i >= -8)
349	return \"movqd %1,%0\";
350	if (i <= 0x1fffffff && i >= -0x20000000)
351	#if defined (GNX_V3) \|\| defined (UTEK_ASM)
352	return \"addr %c1,%0\";
353	#else
354	return \"addr @%c1,%0\";
355	#endif
356	return \"movd %$%1,%0\";
357	}
358	else
359	return output_move_dconst(i, \"%$%1,%0\");
360	}
361	else if (GET_CODE (operands[1]) == CONST && ! flag_pic)
362	{
363	/* Must contain symbols so we don`t know how big it is. In
364	* that case addr might lead to overflow. For PIC symbolic
365	* address loads always have to be done with addr.
366	*/
367	return \"movd %$%1,%0\";
368	}
369	else if (GET_CODE (operands[1]) == REG)
370	{
371	if (REGNO (operands[1]) < 16)
372	return \"movd %1,%0\";
373	else if (REGNO (operands[1]) == FRAME_POINTER_REGNUM)
374	{
375	if (GET_CODE(operands[0]) == REG)
376	return \"sprd fp,%0\";
377	else
378	return \"addr 0(fp),%0\" ;
379	}
380	else if (REGNO (operands[1]) == STACK_POINTER_REGNUM)
381	{
382	if (GET_CODE(operands[0]) == REG)
383	return \"sprd sp,%0\";
384	else
385	return \"addr 0(sp),%0\" ;
386	}
387	else abort ();
388	}
389	else if (GET_CODE (operands[1]) == MEM)
390	return \"movd %1,%0\";
391
392	/* Check if this effective address can be
393	calculated faster by pulling it apart. */
394	if (REG_P (operands[0])
395	&& GET_CODE (operands[1]) == MULT
396	&& GET_CODE (XEXP (operands[1], 1)) == CONST_INT
397	&& (INTVAL (XEXP (operands[1], 1)) == 2
398	\|\| INTVAL (XEXP (operands[1], 1)) == 4))
399	{
400	rtx xoperands[3];
401	xoperands[0] = operands[0];
402	xoperands[1] = XEXP (operands[1], 0);
403	xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1);
404	return output_shift_insn (xoperands);
405	}
406	return \"addr %a1,%0\";
407	}")
408
409	(define_insn "movhi"
410	[(set (match_operand:HI 0 "general_operand" "=g<,*f,g")
411	(match_operand:HI 1 "general_operand" "g,g,*f"))]
412	""
413	"*
414	{
415	if (GET_CODE (operands[1]) == CONST_INT)
416	{
417	short i = INTVAL (operands[1]);
418	if (i <= 7 && i >= -8)
419	{
420	if (INTVAL (operands[1]) > 7)
421	operands[1] =
422	gen_rtx (CONST_INT, VOIDmode, i);
423	return \"movqw %1,%0\";
424	}
425	return \"movw %1,%0\";
426	}
427	else if (FP_REG_P (operands[0]))
428	{
429	if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
430	return \"movwf %1,tos\;movf tos,%0\";
431	else
432	return \"movwf %1,%0\";
433	}
434	else if (FP_REG_P (operands[1]))
435	{
436	if (REG_P (operands[0]))
437	return \"movf %1,tos\;movd tos,%0\";
438	return \"movf %1,%0\";
439	}
440	else
441	return \"movw %1,%0\";
442	}")
443
444	(define_insn "movstricthi"
445	[(set (strict_low_part (match_operand:HI 0 "general_operand" "+r"))
446	(match_operand:HI 1 "general_operand" "g"))]
447	""
448	"*
449	{
450	if (GET_CODE (operands[1]) == CONST_INT
451	&& INTVAL(operands[1]) <= 7 && INTVAL(operands[1]) >= -8)
452	return \"movqw %1,%0\";
453	return \"movw %1,%0\";
454	}")
455
456	(define_insn "movqi"
457	[(set (match_operand:QI 0 "general_operand" "=g<,*f,g")
458	(match_operand:QI 1 "general_operand" "g,g,*f"))]
459	""
460	"*
461	{ if (GET_CODE (operands[1]) == CONST_INT)
462	{
463	char char_val = (char)INTVAL (operands[1]);
464	if (char_val <= 7 && char_val >= -8)
465	{
466	if (INTVAL (operands[1]) > 7)
467	operands[1] =
468	gen_rtx (CONST_INT, VOIDmode, char_val);
469	return \"movqb %1,%0\";
470	}
471	return \"movb %1,%0\";
472	}
473	else if (FP_REG_P (operands[0]))
474	{
475	if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
476	return \"movbf %1,tos\;movf tos,%0\";
477	else
478	return \"movbf %1,%0\";
479	}
480	else if (FP_REG_P (operands[1]))
481	{
482	if (REG_P (operands[0]))
483	return \"movf %1,tos\;movd tos,%0\";
484	return \"movf %1,%0\";
485	}
486	else
487	return \"movb %1,%0\";
488	}")
489
490	(define_insn "movstrictqi"
491	[(set (strict_low_part (match_operand:QI 0 "general_operand" "+r"))
492	(match_operand:QI 1 "general_operand" "g"))]
493	""
494	"*
495	{
496	if (GET_CODE (operands[1]) == CONST_INT
497	&& INTVAL(operands[1]) < 8 && INTVAL(operands[1]) > -9)
498	return \"movqb %1,%0\";
499	return \"movb %1,%0\";
500	}")
501
502	;; This is here to accept 4 arguments and pass the first 3 along
503	;; to the movstrsi1 pattern that really does the work.
504	(define_expand "movstrsi"
505	[(set (match_operand:BLK 0 "general_operand" "=g")
506	(match_operand:BLK 1 "general_operand" "g"))
507	(use (match_operand:SI 2 "general_operand" "rmn"))
508	(match_operand 3 "" "")]
509	""
510	"
511	emit_insn (gen_movstrsi1 (operands[0], operands[1], operands[2]));
512	DONE;
513	")
514
515	;; The definition of this insn does not really explain what it does,
516	;; but it should suffice
517	;; that anything generated as this insn will be recognized as one
518	;; and that it won't successfully combine with anything.
519	(define_insn "movstrsi1"
520	[(set (match_operand:BLK 0 "general_operand" "=g")
521	(match_operand:BLK 1 "general_operand" "g"))
522	(use (match_operand:SI 2 "general_operand" "rmn"))
523	(clobber (reg:SI 0))
524	(clobber (reg:SI 1))
525	(clobber (reg:SI 2))]
526	""
527	"*
528	{
529	if (GET_CODE (operands[0]) != MEM \|\| GET_CODE (operands[1]) != MEM)
530	abort ();
531	operands[0] = XEXP (operands[0], 0);
532	operands[1] = XEXP (operands[1], 0);
533	if (GET_CODE (operands[0]) == MEM)
534	if (GET_CODE (operands[1]) == MEM)
535	output_asm_insn (\"movd %0,r2\;movd %1,r1\", operands);
536	else
537	output_asm_insn (\"movd %0,r2\;addr %a1,r1\", operands);
538	else if (GET_CODE (operands[1]) == MEM)
539	output_asm_insn (\"addr %a0,r2\;movd %1,r1\", operands);
540	else
541	output_asm_insn (\"addr %a0,r2\;addr %a1,r1\", operands);
542
543	#ifdef UTEK_ASM
544	if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) & 0x3) == 0)
545	{
546	operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) >> 2);
547	if ((unsigned) INTVAL (operands[2]) <= 7)
548	return \"movqd %2,r0\;movsd $0\";
549	else
550	return \"movd %2,r0\;movsd $0\";
551	}
552	else
553	{
554	return \"movd %2,r0\;movsb $0\";
555	}
556	#else
557	if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) & 0x3) == 0)
558	{
559	operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) >> 2);
560	if ((unsigned) INTVAL (operands[2]) <= 7)
561	return \"movqd %2,r0\;movsd\";
562	else
563	return \"movd %2,r0\;movsd\";
564	}
565	else
566	{
567	return \"movd %2,r0\;movsb\";
568	}
569	#endif
570	}")
571
572	;; Extension and truncation insns.
573	;; Those for integer source operand
574	;; are ordered widest source type first.
575
576	(define_insn "truncsiqi2"
577	[(set (match_operand:QI 0 "general_operand" "=g<")
578	(truncate:QI (match_operand:SI 1 "nonimmediate_operand" "rmn")))]
579	""
580	"movb %1,%0")
581
582	(define_insn "truncsihi2"
583	[(set (match_operand:HI 0 "general_operand" "=g<")
584	(truncate:HI (match_operand:SI 1 "nonimmediate_operand" "rmn")))]
585	""
586	"movw %1,%0")
587
588	(define_insn "trunchiqi2"
589	[(set (match_operand:QI 0 "general_operand" "=g<")
590	(truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))]
591	""
592	"movb %1,%0")
593
594	(define_insn "extendhisi2"
595	[(set (match_operand:SI 0 "general_operand" "=g<")
596	(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
597	""
598	"movxwd %1,%0")
599
600	(define_insn "extendqihi2"
601	[(set (match_operand:HI 0 "general_operand" "=g<")
602	(sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
603	""
604	"movxbw %1,%0")
605
606	(define_insn "extendqisi2"
607	[(set (match_operand:SI 0 "general_operand" "=g<")
608	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
609	""
610	"movxbd %1,%0")
611
612	(define_insn "extendsfdf2"
613	[(set (match_operand:DF 0 "general_operand" "=fm<")
614	(float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))]
615	"TARGET_32081"
616	"movfl %1,%0")
617
618	(define_insn "truncdfsf2"
619	[(set (match_operand:SF 0 "general_operand" "=fm<")
620	(float_truncate:SF (match_operand:DF 1 "general_operand" "fmF")))]
621	"TARGET_32081"
622	"movlf %1,%0")
623
624	(define_insn "zero_extendhisi2"
625	[(set (match_operand:SI 0 "general_operand" "=g<")
626	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
627	""
628	"movzwd %1,%0")
629
630	(define_insn "zero_extendqihi2"
631	[(set (match_operand:HI 0 "general_operand" "=g<")
632	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
633	""
634	"movzbw %1,%0")
635
636	(define_insn "zero_extendqisi2"
637	[(set (match_operand:SI 0 "general_operand" "=g<")
638	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
639	""
640	"movzbd %1,%0")
641
642	;; Fix-to-float conversion insns.
643	;; Note that the ones that start with SImode come first.
644	;; That is so that an operand that is a CONST_INT
645	;; (and therefore lacks a specific machine mode).
646	;; will be recognized as SImode (which is always valid)
647	;; rather than as QImode or HImode.
648
649	;; Rumor has it that the National part does not correctly convert
650	;; constant ints to floats. This conversion is therefore disabled.
651	;; A register must be used to perform the conversion.
652
653	(define_insn "floatsisf2"
654	[(set (match_operand:SF 0 "general_operand" "=fm<")
655	(float:SF (match_operand:SI 1 "general_operand" "rm")))]
656	"TARGET_32081"
657	"movdf %1,%0")
658
659	(define_insn "floatsidf2"
660	[(set (match_operand:DF 0 "general_operand" "=fm<")
661	(float:DF (match_operand:SI 1 "general_operand" "rm")))]
662	"TARGET_32081"
663	"movdl %1,%0")
664
665	(define_insn "floathisf2"
666	[(set (match_operand:SF 0 "general_operand" "=fm<")
667	(float:SF (match_operand:HI 1 "general_operand" "rm")))]
668	"TARGET_32081"
669	"movwf %1,%0")
670
671	(define_insn "floathidf2"
672	[(set (match_operand:DF 0 "general_operand" "=fm<")
673	(float:DF (match_operand:HI 1 "general_operand" "rm")))]
674	"TARGET_32081"
675	"movwl %1,%0")
676
677	(define_insn "floatqisf2"
678	[(set (match_operand:SF 0 "general_operand" "=fm<")
679	(float:SF (match_operand:QI 1 "general_operand" "rm")))]
680	"TARGET_32081"
681	"movbf %1,%0")
682
683	; Some assemblers warn that this insn doesn't work.
684	; Maybe they know something we don't.
685	;(define_insn "floatqidf2"
686	; [(set (match_operand:DF 0 "general_operand" "=fm<")
687	; (float:DF (match_operand:QI 1 "general_operand" "rm")))]
688	; "TARGET_32081"
689	; "movbl %1,%0")
690
691	;; Float-to-fix conversion insns.
692	;; The sequent compiler always generates "trunc" insns.
693
694	(define_insn "fixsfqi2"
695	[(set (match_operand:QI 0 "general_operand" "=g<")
696	(fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
697	"TARGET_32081"
698	"truncfb %1,%0")
699
700	(define_insn "fixsfhi2"
701	[(set (match_operand:HI 0 "general_operand" "=g<")
702	(fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
703	"TARGET_32081"
704	"truncfw %1,%0")
705
706	(define_insn "fixsfsi2"
707	[(set (match_operand:SI 0 "general_operand" "=g<")
708	(fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
709	"TARGET_32081"
710	"truncfd %1,%0")
711
712	(define_insn "fixdfqi2"
713	[(set (match_operand:QI 0 "general_operand" "=g<")
714	(fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
715	"TARGET_32081"
716	"trunclb %1,%0")
717
718	(define_insn "fixdfhi2"
719	[(set (match_operand:HI 0 "general_operand" "=g<")
720	(fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
721	"TARGET_32081"
722	"trunclw %1,%0")
723
724	(define_insn "fixdfsi2"
725	[(set (match_operand:SI 0 "general_operand" "=g<")
726	(fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
727	"TARGET_32081"
728	"truncld %1,%0")
729
730	;; Unsigned
731
732	(define_insn "fixunssfqi2"
733	[(set (match_operand:QI 0 "general_operand" "=g<")
734	(unsigned_fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
735	"TARGET_32081"
736	"truncfb %1,%0")
737
738	(define_insn "fixunssfhi2"
739	[(set (match_operand:HI 0 "general_operand" "=g<")
740	(unsigned_fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
741	"TARGET_32081"
742	"truncfw %1,%0")
743
744	(define_insn "fixunssfsi2"
745	[(set (match_operand:SI 0 "general_operand" "=g<")
746	(unsigned_fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
747	"TARGET_32081"
748	"truncfd %1,%0")
749
750	(define_insn "fixunsdfqi2"
751	[(set (match_operand:QI 0 "general_operand" "=g<")
752	(unsigned_fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
753	"TARGET_32081"
754	"trunclb %1,%0")
755
756	(define_insn "fixunsdfhi2"
757	[(set (match_operand:HI 0 "general_operand" "=g<")
758	(unsigned_fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
759	"TARGET_32081"
760	"trunclw %1,%0")
761
762	(define_insn "fixunsdfsi2"
763	[(set (match_operand:SI 0 "general_operand" "=g<")
764	(unsigned_fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
765	"TARGET_32081"
766	"truncld %1,%0")
767
768	;;; These are not yet used by GCC
769	(define_insn "fix_truncsfqi2"
770	[(set (match_operand:QI 0 "general_operand" "=g<")
771	(fix:QI (match_operand:SF 1 "general_operand" "fm")))]
772	"TARGET_32081"
773	"truncfb %1,%0")
774
775	(define_insn "fix_truncsfhi2"
776	[(set (match_operand:HI 0 "general_operand" "=g<")
777	(fix:HI (match_operand:SF 1 "general_operand" "fm")))]
778	"TARGET_32081"
779	"truncfw %1,%0")
780
781	(define_insn "fix_truncsfsi2"
782	[(set (match_operand:SI 0 "general_operand" "=g<")
783	(fix:SI (match_operand:SF 1 "general_operand" "fm")))]
784	"TARGET_32081"
785	"truncfd %1,%0")
786
787	(define_insn "fix_truncdfqi2"
788	[(set (match_operand:QI 0 "general_operand" "=g<")
789	(fix:QI (match_operand:DF 1 "general_operand" "fm")))]
790	"TARGET_32081"
791	"trunclb %1,%0")
792
793	(define_insn "fix_truncdfhi2"
794	[(set (match_operand:HI 0 "general_operand" "=g<")
795	(fix:HI (match_operand:DF 1 "general_operand" "fm")))]
796	"TARGET_32081"
797	"trunclw %1,%0")
798
799	(define_insn "fix_truncdfsi2"
800	[(set (match_operand:SI 0 "general_operand" "=g<")
801	(fix:SI (match_operand:DF 1 "general_operand" "fm")))]
802	"TARGET_32081"
803	"truncld %1,%0")
804
805	;;- All kinds of add instructions.
806
807	(define_insn "adddf3"
808	[(set (match_operand:DF 0 "general_operand" "=fm")
809	(plus:DF (match_operand:DF 1 "general_operand" "%0")
810	(match_operand:DF 2 "general_operand" "fmF")))]
811	"TARGET_32081"
812	"addl %2,%0")
813
814
815	(define_insn "addsf3"
816	[(set (match_operand:SF 0 "general_operand" "=fm")
817	(plus:SF (match_operand:SF 1 "general_operand" "%0")
818	(match_operand:SF 2 "general_operand" "fmF")))]
819	"TARGET_32081"
820	"addf %2,%0")
821
822	(define_insn ""
823	[(set (reg:SI 17)
824	(plus:SI (reg:SI 17)
825	(match_operand:SI 0 "immediate_operand" "i")))]
826	"GET_CODE (operands[0]) == CONST_INT"
827	"*
828	{
829	#ifndef SEQUENT_ADJUST_STACK
830	if (TARGET_32532)
831	if (INTVAL (operands[0]) == 8)
832	return \"cmpd tos,tos\";
833	if (TARGET_32532 \|\| TARGET_32332)
834	if (INTVAL (operands[0]) == 4)
835	return \"cmpqd %$0,tos\";
836	#endif
837	if (! TARGET_32532)
838	{
839	if (INTVAL (operands[0]) < 64 && INTVAL (operands[0]) > -64)
840	return \"adjspb %$%n0\";
841	else if (INTVAL (operands[0]) < 8192 && INTVAL (operands[0]) >= -8192)
842	return \"adjspw %$%n0\";
843	}
844	return \"adjspd %$%n0\";
845	}")
846
847	(define_insn ""
848	[(set (match_operand:SI 0 "general_operand" "=g<")
849	(plus:SI (reg:SI 16)
850	(match_operand:SI 1 "immediate_operand" "i")))]
851	"GET_CODE (operands[1]) == CONST_INT"
852	"addr %c1(fp),%0")
853
854	(define_insn ""
855	[(set (match_operand:SI 0 "general_operand" "=g<")
856	(plus:SI (reg:SI 17)
857	(match_operand:SI 1 "immediate_operand" "i")))]
858	"GET_CODE (operands[1]) == CONST_INT"
859	"addr %c1(sp),%0")
860
861	(define_insn "addsi3"
862	[(set (match_operand:SI 0 "general_operand" "=g,=g&<")
863	(plus:SI (match_operand:SI 1 "general_operand" "%0,r")
864	(match_operand:SI 2 "general_operand" "rmn,n")))]
865	""
866	"*
867	{
868	if (which_alternative == 1)
869	{
870	int i = INTVAL (operands[2]);
871	if (NS32K_DISPLACEMENT_P (i))
872	return \"addr %c2(%1),%0\";
873	else
874	return \"movd %1,%0\;addd %2,%0\";
875	}
876	if (GET_CODE (operands[2]) == CONST_INT)
877	{
878	int i = INTVAL (operands[2]);
879
880	if (i <= 7 && i >= -8)
881	return \"addqd %2,%0\";
882	else if (! TARGET_32532 && GET_CODE (operands[0]) == REG
883	&& i <= 0x1fffffff && i >= -0x20000000)
884	return \"addr %c2(%0),%0\";
885	}
886	return \"addd %2,%0\";
887	}")
888
889	(define_insn "addhi3"
890	[(set (match_operand:HI 0 "general_operand" "=g")
891	(plus:HI (match_operand:HI 1 "general_operand" "%0")
892	(match_operand:HI 2 "general_operand" "g")))]
893	""
894	"*
895	{ if (GET_CODE (operands[2]) == CONST_INT)
896	{
897	int i = INTVAL (operands[2]);
898	if (i <= 7 && i >= -8)
899	return \"addqw %2,%0\";
900	}
901	return \"addw %2,%0\";
902	}")
903
904	(define_insn ""
905	[(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
906	(plus:HI (match_operand:HI 1 "general_operand" "0")
907	(match_operand:HI 2 "general_operand" "g")))]
908	""
909	"*
910	{
911	if (GET_CODE (operands[1]) == CONST_INT
912	&& INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
913	return \"addqw %2,%0\";
914	return \"addw %2,%0\";
915	}")
916
917	(define_insn "addqi3"
918	[(set (match_operand:QI 0 "general_operand" "=g")
919	(plus:QI (match_operand:QI 1 "general_operand" "%0")
920	(match_operand:QI 2 "general_operand" "g")))]
921	""
922	"*
923	{ if (GET_CODE (operands[2]) == CONST_INT)
924	{
925	int i = INTVAL (operands[2]);
926	if (i <= 7 && i >= -8)
927	return \"addqb %2,%0\";
928	}
929	return \"addb %2,%0\";
930	}")
931
932	(define_insn ""
933	[(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
934	(plus:QI (match_operand:QI 1 "general_operand" "0")
935	(match_operand:QI 2 "general_operand" "g")))]
936	""
937	"*
938	{
939	if (GET_CODE (operands[1]) == CONST_INT
940	&& INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
941	return \"addqb %2,%0\";
942	return \"addb %2,%0\";
943	}")
944
945	;;- All kinds of subtract instructions.
946
947	(define_insn "subdf3"
948	[(set (match_operand:DF 0 "general_operand" "=fm")
949	(minus:DF (match_operand:DF 1 "general_operand" "0")
950	(match_operand:DF 2 "general_operand" "fmF")))]
951	"TARGET_32081"
952	"subl %2,%0")
953
954	(define_insn "subsf3"
955	[(set (match_operand:SF 0 "general_operand" "=fm")
956	(minus:SF (match_operand:SF 1 "general_operand" "0")
957	(match_operand:SF 2 "general_operand" "fmF")))]
958	"TARGET_32081"
959	"subf %2,%0")
960
961	(define_insn ""
962	[(set (reg:SI 17)
963	(minus:SI (reg:SI 17)
964	(match_operand:SI 0 "immediate_operand" "i")))]
965	"GET_CODE (operands[0]) == CONST_INT"
966	"*
967	{
968	if (! TARGET_32532 && GET_CODE(operands[0]) == CONST_INT
969	&& INTVAL(operands[0]) < 64 && INTVAL(operands[0]) > -64)
970	return \"adjspb %$%0\";
971	return \"adjspd %$%0\";
972	}")
973
974	(define_insn "subsi3"
975	[(set (match_operand:SI 0 "general_operand" "=g")
976	(minus:SI (match_operand:SI 1 "general_operand" "0")
977	(match_operand:SI 2 "general_operand" "rmn")))]
978	""
979	"*
980	{ if (GET_CODE (operands[2]) == CONST_INT)
981	{
982	int i = INTVAL (operands[2]);
983
984	if (i <= 8 && i >= -7)
985	return \"addqd %$%n2,%0\";
986	}
987	return \"subd %2,%0\";
988	}")
989
990	(define_insn "subhi3"
991	[(set (match_operand:HI 0 "general_operand" "=g")
992	(minus:HI (match_operand:HI 1 "general_operand" "0")
993	(match_operand:HI 2 "general_operand" "g")))]
994	""
995	"*
996	{ if (GET_CODE (operands[2]) == CONST_INT)
997	{
998	int i = INTVAL (operands[2]);
999
1000	if (i <= 8 && i >= -7)
1001	return \"addqw %$%n2,%0\";
1002	}
1003	return \"subw %2,%0\";
1004	}")
1005
1006	(define_insn ""
1007	[(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
1008	(minus:HI (match_operand:HI 1 "general_operand" "0")
1009	(match_operand:HI 2 "general_operand" "g")))]
1010	""
1011	"*
1012	{
1013	if (GET_CODE (operands[1]) == CONST_INT
1014	&& INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
1015	return \"addqw %$%n2,%0\";
1016	return \"subw %2,%0\";
1017	}")
1018
1019	(define_insn "subqi3"
1020	[(set (match_operand:QI 0 "general_operand" "=g")
1021	(minus:QI (match_operand:QI 1 "general_operand" "0")
1022	(match_operand:QI 2 "general_operand" "g")))]
1023	""
1024	"*
1025	{ if (GET_CODE (operands[2]) == CONST_INT)
1026	{
1027	int i = INTVAL (operands[2]);
1028
1029	if (i <= 8 && i >= -7)
1030	return \"addqb %$%n2,%0\";
1031	}
1032	return \"subb %2,%0\";
1033	}")
1034
1035	(define_insn ""
1036	[(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
1037	(minus:QI (match_operand:QI 1 "general_operand" "0")
1038	(match_operand:QI 2 "general_operand" "g")))]
1039	""
1040	"*
1041	{
1042	if (GET_CODE (operands[1]) == CONST_INT
1043	&& INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
1044	return \"addqb %$%n2,%0\";
1045	return \"subb %2,%0\";
1046	}")
1047
1048	;;- Multiply instructions.
1049
1050	(define_insn "muldf3"
1051	[(set (match_operand:DF 0 "general_operand" "=fm")
1052	(mult:DF (match_operand:DF 1 "general_operand" "%0")
1053	(match_operand:DF 2 "general_operand" "fmF")))]
1054	"TARGET_32081"
1055	"mull %2,%0")
1056
1057	(define_insn "mulsf3"
1058	[(set (match_operand:SF 0 "general_operand" "=fm")
1059	(mult:SF (match_operand:SF 1 "general_operand" "%0")
1060	(match_operand:SF 2 "general_operand" "fmF")))]
1061	"TARGET_32081"
1062	"mulf %2,%0")
1063
1064	(define_insn "mulsi3"
1065	[(set (match_operand:SI 0 "general_operand" "=g")
1066	(mult:SI (match_operand:SI 1 "general_operand" "%0")
1067	(match_operand:SI 2 "general_operand" "rmn")))]
1068	""
1069	"muld %2,%0")
1070
1071	(define_insn "mulhi3"
1072	[(set (match_operand:HI 0 "general_operand" "=g")
1073	(mult:HI (match_operand:HI 1 "general_operand" "%0")
1074	(match_operand:HI 2 "general_operand" "g")))]
1075	""
1076	"mulw %2,%0")
1077
1078	(define_insn "mulqi3"
1079	[(set (match_operand:QI 0 "general_operand" "=g")
1080	(mult:QI (match_operand:QI 1 "general_operand" "%0")
1081	(match_operand:QI 2 "general_operand" "g")))]
1082	""
1083	"mulb %2,%0")
1084
1085	(define_insn "umulsidi3"
1086	[(set (match_operand:DI 0 "general_operand" "=g")
1087	(mult:DI (zero_extend:DI
1088	(match_operand:SI 1 "nonimmediate_operand" "0"))
1089	(zero_extend:DI
1090	(match_operand:SI 2 "nonimmediate_operand" "rmn"))))]
1091	""
1092	"meid %2,%0")
1093
1094	;;- Divide instructions.
1095
1096	(define_insn "divdf3"
1097	[(set (match_operand:DF 0 "general_operand" "=fm")
1098	(div:DF (match_operand:DF 1 "general_operand" "0")
1099	(match_operand:DF 2 "general_operand" "fmF")))]
1100	"TARGET_32081"
1101	"divl %2,%0")
1102
1103	(define_insn "divsf3"
1104	[(set (match_operand:SF 0 "general_operand" "=fm")
1105	(div:SF (match_operand:SF 1 "general_operand" "0")
1106	(match_operand:SF 2 "general_operand" "fmF")))]
1107	"TARGET_32081"
1108	"divf %2,%0")
1109
1110	(define_insn "divsi3"
1111	[(set (match_operand:SI 0 "general_operand" "=g")
1112	(div:SI (match_operand:SI 1 "general_operand" "0")
1113	(match_operand:SI 2 "general_operand" "rmn")))]
1114	""
1115	"quod %2,%0")
1116
1117	(define_insn "divhi3"
1118	[(set (match_operand:HI 0 "general_operand" "=g")
1119	(div:HI (match_operand:HI 1 "general_operand" "0")
1120	(match_operand:HI 2 "general_operand" "g")))]
1121	""
1122	"quow %2,%0")
1123
1124	(define_insn "divqi3"
1125	[(set (match_operand:QI 0 "general_operand" "=g")
1126	(div:QI (match_operand:QI 1 "general_operand" "0")
1127	(match_operand:QI 2 "general_operand" "g")))]
1128	""
1129	"quob %2,%0")
1130
1131	(define_insn "udivsi3"
1132	[(set (match_operand:SI 0 "register_operand" "=r")
1133	(udiv:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1134	(match_operand:SI 2 "general_operand" "rmn")))]
1135	""
1136	"*
1137	{
1138	operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1139	return \"deid %2,%0\;movd %1,%0\";
1140	}")
1141
1142	(define_insn "udivhi3"
1143	[(set (match_operand:HI 0 "register_operand" "=r")
1144	(udiv:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1145	(match_operand:HI 2 "general_operand" "g")))]
1146	""
1147	"*
1148	{
1149	operands[1] = gen_rtx (REG, HImode, REGNO (operands[0]) + 1);
1150	return \"deiw %2,%0\;movw %1,%0\";
1151	}")
1152
1153	(define_insn "udivqi3"
1154	[(set (match_operand:QI 0 "register_operand" "=r")
1155	(udiv:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1156	(match_operand:QI 2 "general_operand" "g")))]
1157	""
1158	"*
1159	{
1160	operands[1] = gen_rtx (REG, QImode, REGNO (operands[0]) + 1);
1161	return \"deib %2,%0\;movb %1,%0\";
1162	}")
1163
1164	;; Remainder instructions.
1165
1166	(define_insn "modsi3"
1167	[(set (match_operand:SI 0 "general_operand" "=g")
1168	(mod:SI (match_operand:SI 1 "general_operand" "0")
1169	(match_operand:SI 2 "general_operand" "rmn")))]
1170	""
1171	"remd %2,%0")
1172
1173	(define_insn "modhi3"
1174	[(set (match_operand:HI 0 "general_operand" "=g")
1175	(mod:HI (match_operand:HI 1 "general_operand" "0")
1176	(match_operand:HI 2 "general_operand" "g")))]
1177	""
1178	"remw %2,%0")
1179
1180	(define_insn "modqi3"
1181	[(set (match_operand:QI 0 "general_operand" "=g")
1182	(mod:QI (match_operand:QI 1 "general_operand" "0")
1183	(match_operand:QI 2 "general_operand" "g")))]
1184	""
1185	"remb %2,%0")
1186
1187	(define_insn "umodsi3"
1188	[(set (match_operand:SI 0 "register_operand" "=r")
1189	(umod:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1190	(match_operand:SI 2 "general_operand" "rmn")))]
1191	""
1192	"deid %2,%0")
1193
1194	(define_insn "umodhi3"
1195	[(set (match_operand:HI 0 "register_operand" "=r")
1196	(umod:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1197	(match_operand:HI 2 "general_operand" "g")))]
1198	""
1199	"deiw %2,%0")
1200
1201	(define_insn "umodqi3"
1202	[(set (match_operand:QI 0 "register_operand" "=r")
1203	(umod:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1204	(match_operand:QI 2 "general_operand" "g")))]
1205	""
1206	"deib %2,%0")
1207
1208	; This isn't be usable in its current form.
1209	;(define_insn "udivmoddisi4"
1210	; [(set (subreg:SI (match_operand:DI 0 "general_operand" "=r") 1)
1211	; (udiv:SI (match_operand:DI 1 "general_operand" "0")
1212	; (match_operand:SI 2 "general_operand" "rmn")))
1213	; (set (subreg:SI (match_dup 0) 0)
1214	; (umod:SI (match_dup 1) (match_dup 2)))]
1215	; ""
1216	; "deid %2,%0")
1217
1218	;;- Logical Instructions: AND
1219
1220	(define_insn "andsi3"
1221	[(set (match_operand:SI 0 "general_operand" "=g")
1222	(and:SI (match_operand:SI 1 "general_operand" "%0")
1223	(match_operand:SI 2 "general_operand" "rmn")))]
1224	""
1225	"*
1226	{
1227	if (GET_CODE (operands[2]) == CONST_INT)
1228	{
1229	if ((INTVAL (operands[2]) \| 0xff) == 0xffffffff)
1230	{
1231	if (INTVAL (operands[2]) == 0xffffff00)
1232	return \"movqb %$0,%0\";
1233	else
1234	{
1235	operands[2] = gen_rtx (CONST_INT, VOIDmode,
1236	INTVAL (operands[2]) & 0xff);
1237	return \"andb %2,%0\";
1238	}
1239	}
1240	if ((INTVAL (operands[2]) \| 0xffff) == 0xffffffff)
1241	{
1242	if (INTVAL (operands[2]) == 0xffff0000)
1243	return \"movqw %$0,%0\";
1244	else
1245	{
1246	operands[2] = gen_rtx (CONST_INT, VOIDmode,
1247	INTVAL (operands[2]) & 0xffff);
1248	return \"andw %2,%0\";
1249	}
1250	}
1251	}
1252	return \"andd %2,%0\";
1253	}")
1254
1255	(define_insn "andhi3"
1256	[(set (match_operand:HI 0 "general_operand" "=g")
1257	(and:HI (match_operand:HI 1 "general_operand" "%0")
1258	(match_operand:HI 2 "general_operand" "g")))]
1259	""
1260	"*
1261	{
1262	if (GET_CODE (operands[2]) == CONST_INT
1263	&& (INTVAL (operands[2]) \| 0xff) == 0xffffffff)
1264	{
1265	if (INTVAL (operands[2]) == 0xffffff00)
1266	return \"movqb %$0,%0\";
1267	else
1268	{
1269	operands[2] = gen_rtx (CONST_INT, VOIDmode,
1270	INTVAL (operands[2]) & 0xff);
1271	return \"andb %2,%0\";
1272	}
1273	}
1274	return \"andw %2,%0\";
1275	}")
1276
1277	(define_insn "andqi3"
1278	[(set (match_operand:QI 0 "general_operand" "=g")
1279	(and:QI (match_operand:QI 1 "general_operand" "%0")
1280	(match_operand:QI 2 "general_operand" "g")))]
1281	""
1282	"andb %2,%0")
1283
1284	(define_insn ""
1285	[(set (match_operand:SI 0 "general_operand" "=g")
1286	(and:SI (not:SI (match_operand:SI 1 "general_operand" "rmn"))
1287	(match_operand:SI 2 "general_operand" "0")))]
1288	""
1289	"bicd %1,%0")
1290
1291	(define_insn ""
1292	[(set (match_operand:HI 0 "general_operand" "=g")
1293	(and:HI (not:HI (match_operand:HI 1 "general_operand" "g"))
1294	(match_operand:HI 2 "general_operand" "0")))]
1295	""
1296	"bicw %1,%0")
1297
1298	(define_insn ""
1299	[(set (match_operand:QI 0 "general_operand" "=g")
1300	(and:QI (not:QI (match_operand:QI 1 "general_operand" "g"))
1301	(match_operand:QI 2 "general_operand" "0")))]
1302	""
1303	"bicb %1,%0")
1304
1305	;;- Bit set instructions.
1306
1307	(define_insn "iorsi3"
1308	[(set (match_operand:SI 0 "general_operand" "=g")
1309	(ior:SI (match_operand:SI 1 "general_operand" "%0")
1310	(match_operand:SI 2 "general_operand" "rmn")))]
1311	""
1312	"*
1313	{
1314	if (GET_CODE (operands[2]) == CONST_INT) {
1315	if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1316	return \"orb %2,%0\";
1317	if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1318	return \"orw %2,%0\";
1319	}
1320	return \"ord %2,%0\";
1321	}")
1322
1323	(define_insn "iorhi3"
1324	[(set (match_operand:HI 0 "general_operand" "=g")
1325	(ior:HI (match_operand:HI 1 "general_operand" "%0")
1326	(match_operand:HI 2 "general_operand" "g")))]
1327	""
1328	"*
1329	{
1330	if (GET_CODE(operands[2]) == CONST_INT &&
1331	(INTVAL(operands[2]) & 0xffffff00) == 0)
1332	return \"orb %2,%0\";
1333	return \"orw %2,%0\";
1334	}")
1335
1336	(define_insn "iorqi3"
1337	[(set (match_operand:QI 0 "general_operand" "=g")
1338	(ior:QI (match_operand:QI 1 "general_operand" "%0")
1339	(match_operand:QI 2 "general_operand" "g")))]
1340	""
1341	"orb %2,%0")
1342
1343	;;- xor instructions.
1344
1345	(define_insn "xorsi3"
1346	[(set (match_operand:SI 0 "general_operand" "=g")
1347	(xor:SI (match_operand:SI 1 "general_operand" "%0")
1348	(match_operand:SI 2 "general_operand" "rmn")))]
1349	""
1350	"*
1351	{
1352	if (GET_CODE (operands[2]) == CONST_INT) {
1353	if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1354	return \"xorb %2,%0\";
1355	if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1356	return \"xorw %2,%0\";
1357	}
1358	return \"xord %2,%0\";
1359	}")
1360
1361	(define_insn "xorhi3"
1362	[(set (match_operand:HI 0 "general_operand" "=g")
1363	(xor:HI (match_operand:HI 1 "general_operand" "%0")
1364	(match_operand:HI 2 "general_operand" "g")))]
1365	""
1366	"*
1367	{
1368	if (GET_CODE(operands[2]) == CONST_INT &&
1369	(INTVAL(operands[2]) & 0xffffff00) == 0)
1370	return \"xorb %2,%0\";
1371	return \"xorw %2,%0\";
1372	}")
1373
1374	(define_insn "xorqi3"
1375	[(set (match_operand:QI 0 "general_operand" "=g")
1376	(xor:QI (match_operand:QI 1 "general_operand" "%0")
1377	(match_operand:QI 2 "general_operand" "g")))]
1378	""
1379	"xorb %2,%0")
1380
1381	(define_insn "negdf2"
1382	[(set (match_operand:DF 0 "general_operand" "=fm<")
1383	(neg:DF (match_operand:DF 1 "general_operand" "fmF")))]
1384	"TARGET_32081"
1385	"negl %1,%0")
1386
1387	(define_insn "negsf2"
1388	[(set (match_operand:SF 0 "general_operand" "=fm<")
1389	(neg:SF (match_operand:SF 1 "general_operand" "fmF")))]
1390	"TARGET_32081"
1391	"negf %1,%0")
1392
1393	(define_insn "negsi2"
1394	[(set (match_operand:SI 0 "general_operand" "=g<")
1395	(neg:SI (match_operand:SI 1 "general_operand" "rmn")))]
1396	""
1397	"negd %1,%0")
1398
1399	(define_insn "neghi2"
1400	[(set (match_operand:HI 0 "general_operand" "=g<")
1401	(neg:HI (match_operand:HI 1 "general_operand" "g")))]
1402	""
1403	"negw %1,%0")
1404
1405	(define_insn "negqi2"
1406	[(set (match_operand:QI 0 "general_operand" "=g<")
1407	(neg:QI (match_operand:QI 1 "general_operand" "g")))]
1408	""
1409	"negb %1,%0")
1410
1411	(define_insn "one_cmplsi2"
1412	[(set (match_operand:SI 0 "general_operand" "=g<")
1413	(not:SI (match_operand:SI 1 "general_operand" "rmn")))]
1414	""
1415	"comd %1,%0")
1416
1417	(define_insn "one_cmplhi2"
1418	[(set (match_operand:HI 0 "general_operand" "=g<")
1419	(not:HI (match_operand:HI 1 "general_operand" "g")))]
1420	""
1421	"comw %1,%0")
1422
1423	(define_insn "one_cmplqi2"
1424	[(set (match_operand:QI 0 "general_operand" "=g<")
1425	(not:QI (match_operand:QI 1 "general_operand" "g")))]
1426	""
1427	"comb %1,%0")
1428
1429	;; arithmetic left and right shift operations
1430	;; on the 32532 we will always use lshd for arithmetic left shifts,
1431	;; because it is three times faster. Broken programs which
1432	;; use negative shift counts are probably broken differently
1433	;; than elsewhere.
1434
1435	;; alternative 0 never matches on the 32532
1436	(define_insn "ashlsi3"
1437	[(set (match_operand:SI 0 "general_operand" "=g,g")
1438	(ashift:SI (match_operand:SI 1 "general_operand" "r,0")
1439	(match_operand:SI 2 "general_operand" "I,rmn")))]
1440	""
1441	"*
1442	{ if (TARGET_32532)
1443	return \"lshd %2,%0\";
1444	else
1445	return output_shift_insn (operands);
1446	}")
1447
1448	(define_insn "ashlhi3"
1449	[(set (match_operand:HI 0 "general_operand" "=g")
1450	(ashift:HI (match_operand:HI 1 "general_operand" "0")
1451	(match_operand:SI 2 "general_operand" "rmn")))]
1452	""
1453	"*
1454	{ if (GET_CODE (operands[2]) == CONST_INT)
1455	{
1456	if (INTVAL (operands[2]) == 1)
1457	return \"addw %0,%0\";
1458	else if (! TARGET_32532 && INTVAL (operands[2]) == 2)
1459	return \"addw %0,%0\;addw %0,%0\";
1460	}
1461	if (TARGET_32532)
1462	return \"lshw %2,%0\";
1463	else
1464	return \"ashw %2,%0\";
1465	}")
1466
1467	(define_insn "ashlqi3"
1468	[(set (match_operand:QI 0 "general_operand" "=g")
1469	(ashift:QI (match_operand:QI 1 "general_operand" "0")
1470	(match_operand:SI 2 "general_operand" "rmn")))]
1471	""
1472	"*
1473	{ if (GET_CODE (operands[2]) == CONST_INT)
1474	{
1475	if (INTVAL (operands[2]) == 1)
1476	return \"addb %0,%0\";
1477	else if (! TARGET_32532 && INTVAL (operands[2]) == 2)
1478	return \"addb %0,%0\;addb %0,%0\";
1479	}
1480	if (TARGET_32532)
1481	return \"lshb %2,%0\";
1482	else
1483	return \"ashb %2,%0\";
1484	}")
1485
1486	;; Arithmetic right shift on the 32k works by negating the shift count.
1487	(define_expand "ashrsi3"
1488	[(set (match_operand:SI 0 "general_operand" "=g")
1489	(ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1490	(match_operand:SI 2 "general_operand" "g")))]
1491	""
1492	"
1493	{
1494	if (GET_CODE (operands[2]) != CONST_INT)
1495	operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1496	}")
1497
1498	(define_insn ""
1499	[(set (match_operand:SI 0 "general_operand" "=g")
1500	(ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
1501	(match_operand:SI 2 "immediate_operand" "i")))]
1502	""
1503	"ashd %$%n2,%0")
1504
1505	(define_insn ""
1506	[(set (match_operand:SI 0 "general_operand" "=g")
1507	(ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
1508	(neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1509	""
1510	"ashd %2,%0")
1511
1512	(define_expand "ashrhi3"
1513	[(set (match_operand:HI 0 "general_operand" "=g")
1514	(ashiftrt:HI (match_operand:HI 1 "general_operand" "g")
1515	(match_operand:SI 2 "general_operand" "g")))]
1516	""
1517	"
1518	{
1519	if (GET_CODE (operands[2]) != CONST_INT)
1520	operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1521	}")
1522
1523	(define_insn ""
1524	[(set (match_operand:HI 0 "general_operand" "=g")
1525	(ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
1526	(match_operand:SI 2 "immediate_operand" "i")))]
1527	""
1528	"ashw %$%n2,%0")
1529
1530	(define_insn ""
1531	[(set (match_operand:HI 0 "general_operand" "=g")
1532	(ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
1533	(neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1534	""
1535	"ashw %2,%0")
1536
1537	(define_expand "ashrqi3"
1538	[(set (match_operand:QI 0 "general_operand" "=g")
1539	(ashiftrt:QI (match_operand:QI 1 "general_operand" "g")
1540	(match_operand:SI 2 "general_operand" "g")))]
1541	""
1542	"
1543	{
1544	if (GET_CODE (operands[2]) != CONST_INT)
1545	operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1546	}")
1547
1548	(define_insn ""
1549	[(set (match_operand:QI 0 "general_operand" "=g")
1550	(ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
1551	(match_operand:SI 2 "immediate_operand" "i")))]
1552	""
1553	"ashb %$%n2,%0")
1554
1555	(define_insn ""
1556	[(set (match_operand:QI 0 "general_operand" "=g")
1557	(ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
1558	(neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1559	""
1560	"ashb %2,%0")
1561
1562	;; logical shift instructions
1563
1564	;; Logical right shift on the 32k works by negating the shift count.
1565	(define_expand "lshrsi3"
1566	[(set (match_operand:SI 0 "general_operand" "=g")
1567	(lshiftrt:SI (match_operand:SI 1 "general_operand" "g")
1568	(match_operand:SI 2 "general_operand" "g")))]
1569	""
1570	"
1571	{
1572	if (GET_CODE (operands[2]) != CONST_INT)
1573	operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1574	}")
1575
1576	(define_insn ""
1577	[(set (match_operand:SI 0 "general_operand" "=g")
1578	(lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
1579	(match_operand:SI 2 "immediate_operand" "i")))]
1580	""
1581	"lshd %$%n2,%0")
1582
1583	(define_insn ""
1584	[(set (match_operand:SI 0 "general_operand" "=g")
1585	(lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
1586	(neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1587	""
1588	"lshd %2,%0")
1589
1590	(define_expand "lshrhi3"
1591	[(set (match_operand:HI 0 "general_operand" "=g")
1592	(lshiftrt:HI (match_operand:HI 1 "general_operand" "g")
1593	(match_operand:SI 2 "general_operand" "g")))]
1594	""
1595	"
1596	{
1597	if (GET_CODE (operands[2]) != CONST_INT)
1598	operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1599	}")
1600
1601	(define_insn ""
1602	[(set (match_operand:HI 0 "general_operand" "=g")
1603	(lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
1604	(match_operand:SI 2 "immediate_operand" "i")))]
1605	""
1606	"lshw %$%n2,%0")
1607
1608	(define_insn ""
1609	[(set (match_operand:HI 0 "general_operand" "=g")
1610	(lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
1611	(neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1612	""
1613	"lshw %2,%0")
1614
1615	(define_expand "lshrqi3"
1616	[(set (match_operand:QI 0 "general_operand" "=g")
1617	(lshiftrt:QI (match_operand:QI 1 "general_operand" "g")
1618	(match_operand:SI 2 "general_operand" "g")))]
1619	""
1620	"
1621	{
1622	if (GET_CODE (operands[2]) != CONST_INT)
1623	operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1624	}")
1625
1626	(define_insn ""
1627	[(set (match_operand:QI 0 "general_operand" "=g")
1628	(lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
1629	(match_operand:SI 2 "immediate_operand" "i")))]
1630	""
1631	"lshb %$%n2,%0")
1632
1633	(define_insn ""
1634	[(set (match_operand:QI 0 "general_operand" "=g")
1635	(lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
1636	(neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1637	""
1638	"lshb %2,%0")
1639
1640	;; Rotate instructions
1641
1642	(define_insn "rotlsi3"
1643	[(set (match_operand:SI 0 "general_operand" "=g")
1644	(rotate:SI (match_operand:SI 1 "general_operand" "0")
1645	(match_operand:SI 2 "general_operand" "rmn")))]
1646	""
1647	"rotd %2,%0")
1648
1649	(define_insn "rotlhi3"
1650	[(set (match_operand:HI 0 "general_operand" "=g")
1651	(rotate:HI (match_operand:HI 1 "general_operand" "0")
1652	(match_operand:SI 2 "general_operand" "rmn")))]
1653	""
1654	"rotw %2,%0")
1655
1656	(define_insn "rotlqi3"
1657	[(set (match_operand:QI 0 "general_operand" "=g")
1658	(rotate:QI (match_operand:QI 1 "general_operand" "0")
1659	(match_operand:SI 2 "general_operand" "rmn")))]
1660	""
1661	"rotb %2,%0")
1662
1663	;; Right rotate on the 32k works by negating the shift count.
1664	(define_expand "rotrsi3"
1665	[(set (match_operand:SI 0 "general_operand" "=g")
1666	(rotatert:SI (match_operand:SI 1 "general_operand" "g")
1667	(match_operand:SI 2 "general_operand" "g")))]
1668	""
1669	"
1670	{
1671	if (GET_CODE (operands[2]) != CONST_INT)
1672	operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1673	}")
1674
1675	(define_insn ""
1676	[(set (match_operand:SI 0 "general_operand" "=g")
1677	(rotatert:SI (match_operand:SI 1 "general_operand" "0")
1678	(match_operand:SI 2 "immediate_operand" "i")))]
1679	""
1680	"rotd %$%n2,%0")
1681
1682	(define_insn ""
1683	[(set (match_operand:SI 0 "general_operand" "=g")
1684	(rotatert:SI (match_operand:SI 1 "general_operand" "0")
1685	(neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1686	""
1687	"rotd %2,%0")
1688
1689	(define_expand "rotrhi3"
1690	[(set (match_operand:HI 0 "general_operand" "=g")
1691	(rotatert:HI (match_operand:HI 1 "general_operand" "g")
1692	(match_operand:SI 2 "general_operand" "g")))]
1693	""
1694	"
1695	{
1696	if (GET_CODE (operands[2]) != CONST_INT)
1697	operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1698	}")
1699
1700	(define_insn ""
1701	[(set (match_operand:HI 0 "general_operand" "=g")
1702	(rotatert:HI (match_operand:HI 1 "general_operand" "0")
1703	(match_operand:SI 2 "immediate_operand" "i")))]
1704	""
1705	"rotw %$%n2,%0")
1706
1707	(define_insn ""
1708	[(set (match_operand:HI 0 "general_operand" "=g")
1709	(rotatert:HI (match_operand:HI 1 "general_operand" "0")
1710	(neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1711	""
1712	"rotw %2,%0")
1713
1714	(define_expand "rotrqi3"
1715	[(set (match_operand:QI 0 "general_operand" "=g")
1716	(rotatert:QI (match_operand:QI 1 "general_operand" "g")
1717	(match_operand:SI 2 "general_operand" "g")))]
1718	""
1719	"
1720	{
1721	if (GET_CODE (operands[2]) != CONST_INT)
1722	operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1723	}")
1724
1725	(define_insn ""
1726	[(set (match_operand:QI 0 "general_operand" "=g")
1727	(rotatert:QI (match_operand:QI 1 "general_operand" "0")
1728	(match_operand:SI 2 "immediate_operand" "i")))]
1729	""
1730	"rotb %$%n2,%0")
1731
1732	(define_insn ""
1733	[(set (match_operand:QI 0 "general_operand" "=g")
1734	(rotatert:QI (match_operand:QI 1 "general_operand" "0")
1735	(neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1736	""
1737	"rotb %2,%0")
1738
1739	;;- load or push effective address
1740	;; These come after the move, add, and multiply patterns
1741	;; because we don't want pushl $1 turned into pushad 1.
1742
1743	(define_insn ""
1744	[(set (match_operand:SI 0 "general_operand" "=g<")
1745	(match_operand:QI 1 "address_operand" "p"))]
1746	""
1747	"*
1748	{
1749	if (REG_P (operands[0])
1750	&& GET_CODE (operands[1]) == MULT
1751	&& GET_CODE (XEXP (operands[1], 1)) == CONST_INT
1752	&& (INTVAL (XEXP (operands[1], 1)) == 2
1753	\|\| INTVAL (XEXP (operands[1], 1)) == 4))
1754	{
1755	rtx xoperands[3];
1756	xoperands[0] = operands[0];
1757	xoperands[1] = XEXP (operands[1], 0);
1758	xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1);
1759	return output_shift_insn (xoperands);
1760	}
1761	return \"addr %a1,%0\";
1762	}")
1763
1764	;;; Index insns. These are about the same speed as multiply-add counterparts.
1765	;;; but slower then using power-of-2 shifts if we can use them
1766	;
1767	;(define_insn ""
1768	; [(set (match_operand:SI 0 "register_operand" "=r")
1769	; (plus:SI (match_operand:SI 1 "general_operand" "rmn")
1770	; (mult:SI (match_operand:SI 2 "register_operand" "0")
1771	; (plus:SI (match_operand:SI 3 "general_operand" "rmn") (const_int 1)))))]
1772	; "GET_CODE (operands[3]) != CONST_INT \|\| INTVAL (operands[3]) > 8"
1773	; "indexd %0,%3,%1")
1774	;
1775	;(define_insn ""
1776	; [(set (match_operand:SI 0 "register_operand" "=r")
1777	; (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
1778	; (plus:SI (match_operand:SI 2 "general_operand" "rmn") (const_int 1)))
1779	; (match_operand:SI 3 "general_operand" "rmn")))]
1780	; "GET_CODE (operands[2]) != CONST_INT \|\| INTVAL (operands[2]) > 8"
1781	; "indexd %0,%2,%3")
1782
1783	;; Set, Clear, and Invert bit
1784
1785	(define_insn ""
1786	[(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+g")
1787	(const_int 1)
1788	(match_operand:SI 1 "general_operand" "rmn"))
1789	(const_int 1))]
1790	""
1791	"sbitd %1,%0")
1792
1793	(define_insn ""
1794	[(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+g")
1795	(const_int 1)
1796	(match_operand:SI 1 "general_operand" "rmn"))
1797	(const_int 0))]
1798	""
1799	"cbitd %1,%0")
1800
1801	(define_insn ""
1802	[(set (match_operand:SI 0 "general_operand" "+g")
1803	(xor:SI (ashift:SI (const_int 1)
1804	(match_operand:SI 1 "general_operand" "rmn"))
1805	(match_dup 0)))]
1806	""
1807	"ibitd %1,%0")
1808
1809	(define_insn ""
1810	[(set (match_operand:QI 0 "general_operand" "=g")
1811	(xor:QI (subreg:QI
1812	(ashift:SI (const_int 1)
1813	(match_operand:QI 1 "general_operand" "rmn")) 0)
1814	(match_dup 0)))]
1815	""
1816	"ibitb %1,%0")
1817
1818	;; Recognize jbs and jbc instructions.
1819
1820	(define_insn ""
1821	[(set (cc0)
1822	(zero_extract (match_operand:SI 0 "general_operand" "rm")
1823	(const_int 1)
1824	(match_operand:SI 1 "general_operand" "g")))]
1825	""
1826	"*
1827	{ cc_status.flags = CC_Z_IN_F;
1828	return \"tbitd %1,%0\";
1829	}")
1830
1831	;; extract(base, width, offset)
1832	;; Signed bitfield extraction is not supported in hardware on the
1833	;; NS 32032. It is therefore better to let GCC figure out a
1834	;; good strategy for generating the proper instruction sequence
1835	;; and represent it as rtl.
1836
1837	;; Optimize the case of extracting a byte or word from a register.
1838	;; Otherwise we must load a register with the offset of the
1839	;; chunk we want, and perform an extract insn (each of which
1840	;; is very expensive). Since we use the stack to do our bit-twiddling
1841	;; we cannot use it for a destination. Perhaps things are fast
1842	;; enough on the 32532 that such hacks are not needed.
1843
1844	(define_insn ""
1845	[(set (match_operand:SI 0 "general_operand" "=ro")
1846	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
1847	(match_operand:SI 2 "const_int_operand" "i")
1848	(match_operand:SI 3 "const_int_operand" "i")))]
1849	"(INTVAL (operands[2]) == 8 \|\| INTVAL (operands[2]) == 16)
1850	&& (INTVAL (operands[3]) == 8 \|\| INTVAL (operands[3]) == 16 \|\| INTVAL (operands[3]) == 24)"
1851	"*
1852	{
1853	output_asm_insn (\"movd %1,tos\", operands);
1854	if (INTVAL (operands[2]) == 16)
1855	{
1856	if (INTVAL (operands[3]) == 8)
1857	output_asm_insn (\"movzwd 1(sp),%0\", operands);
1858	else
1859	output_asm_insn (\"movzwd 2(sp),%0\", operands);
1860	}
1861	else
1862	{
1863	if (INTVAL (operands[3]) == 8)
1864	output_asm_insn (\"movzbd 1(sp),%0\", operands);
1865	else if (INTVAL (operands[3]) == 16)
1866	output_asm_insn (\"movzbd 2(sp),%0\", operands);
1867	else
1868	output_asm_insn (\"movzbd 3(sp),%0\", operands);
1869	}
1870	if (TARGET_32532 \|\| TARGET_32332)
1871	return \"cmpqd %$0,tos\";
1872	else
1873	return \"adjspb %$-4\";
1874	}")
1875
1876	;; The exts/ext instructions have the problem that they always access
1877	;; 32 bits even if the bitfield is smaller. For example the instruction
1878	;; extsd 7(r1),r0,2,5
1879	;; would read not only at address 7(r1) but also at 8(r1) to 10(r1).
1880	;; If these addresses are in a different (unmapped) page a memory fault
1881	;; is the result.
1882	;;
1883	;; Timing considerations:
1884	;; movd 0(r1),r0 3 bytes
1885	;; lshd -26,r0 4
1886	;; andd 0x1f,r0 5
1887	;; takes about 13 cycles on the 532 while
1888	;; extsd 7(r1),r0,2,5 5 bytes
1889	;; takes about 21 cycles.
1890	;;
1891	;; The inss/ins instructions suffer from the same problem.
1892	;;
1893	;; A machine specific option (-mbitfield/-mnobitfield) is used
1894	;; to allow/disallow the use of these instructions.
1895
1896	(define_insn ""
1897	[(set (match_operand:SI 0 "general_operand" "=g<")
1898	(zero_extract:SI (match_operand:SI 1 "register_operand" "g")
1899	(match_operand:SI 2 "const_int_operand" "i")
1900	(match_operand:SI 3 "general_operand" "rK")))]
1901	"TARGET_BITFIELD"
1902	"*
1903	{ if (GET_CODE (operands[3]) == CONST_INT)
1904	return \"extsd %1,%0,%3,%2\";
1905	else return \"extd %3,%1,%0,%2\";
1906	}")
1907
1908	(define_insn "extzv"
1909	[(set (match_operand:SI 0 "general_operand" "=g<")
1910	(zero_extract:SI (match_operand:QI 1 "general_operand" "g")
1911	(match_operand:SI 2 "const_int_operand" "i")
1912	(match_operand:SI 3 "general_operand" "rK")))]
1913	"TARGET_BITFIELD"
1914	"*
1915	{ if (GET_CODE (operands[3]) == CONST_INT)
1916	return \"extsd %1,%0,%3,%2\";
1917	else return \"extd %3,%1,%0,%2\";
1918	}")
1919
1920	(define_insn ""
1921	[(set (zero_extract:SI (match_operand:SI 0 "memory_operand" "+o")
1922	(match_operand:SI 1 "const_int_operand" "i")
1923	(match_operand:SI 2 "general_operand" "rn"))
1924	(match_operand:SI 3 "general_operand" "rm"))]
1925	"TARGET_BITFIELD"
1926	"*
1927	{ if (GET_CODE (operands[2]) == CONST_INT)
1928	{
1929	if (INTVAL (operands[2]) >= 8)
1930	{
1931	operands[0] = adj_offsettable_operand (operands[0],
1932	INTVAL (operands[2]) / 8);
1933	operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) % 8);
1934	}
1935	if (INTVAL (operands[1]) <= 8)
1936	return \"inssb %3,%0,%2,%1\";
1937	else if (INTVAL (operands[1]) <= 16)
1938	return \"inssw %3,%0,%2,%1\";
1939	else
1940	return \"inssd %3,%0,%2,%1\";
1941	}
1942	return \"insd %2,%3,%0,%1\";
1943	}")
1944
1945	(define_insn ""
1946	[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
1947	(match_operand:SI 1 "const_int_operand" "i")
1948	(match_operand:SI 2 "general_operand" "rK"))
1949	(match_operand:SI 3 "general_operand" "rm"))]
1950	"TARGET_BITFIELD"
1951	"*
1952	{ if (GET_CODE (operands[2]) == CONST_INT)
1953	if (INTVAL (operands[1]) <= 8)
1954	return \"inssb %3,%0,%2,%1\";
1955	else if (INTVAL (operands[1]) <= 16)
1956	return \"inssw %3,%0,%2,%1\";
1957	else
1958	return \"inssd %3,%0,%2,%1\";
1959	return \"insd %2,%3,%0,%1\";
1960	}")
1961
1962	(define_insn "insv"
1963	[(set (zero_extract:SI (match_operand:QI 0 "general_operand" "+g")
1964	(match_operand:SI 1 "const_int_operand" "i")
1965	(match_operand:SI 2 "general_operand" "rK"))
1966	(match_operand:SI 3 "general_operand" "rm"))]
1967	"TARGET_BITFIELD"
1968	"*
1969	{ if (GET_CODE (operands[2]) == CONST_INT)
1970	if (INTVAL (operands[1]) <= 8)
1971	return \"inssb %3,%0,%2,%1\";
1972	else if (INTVAL (operands[1]) <= 16)
1973	return \"inssw %3,%0,%2,%1\";
1974	else
1975	return \"inssd %3,%0,%2,%1\";
1976	return \"insd %2,%3,%0,%1\";
1977	}")
1978
1979
1980	(define_insn "jump"
1981	[(set (pc)
1982	(label_ref (match_operand 0 "" "")))]
1983	""
1984	"br %l0")
1985
1986	(define_insn "beq"
1987	[(set (pc)
1988	(if_then_else (eq (cc0)
1989	(const_int 0))
1990	(label_ref (match_operand 0 "" ""))
1991	(pc)))]
1992	""
1993	"*
1994	{ if (cc_prev_status.flags & CC_Z_IN_F)
1995	return \"bfc %l0\";
1996	else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
1997	return \"bfs %l0\";
1998	else return \"beq %l0\";
1999	}")
2000
2001	(define_insn "bne"
2002	[(set (pc)
2003	(if_then_else (ne (cc0)
2004	(const_int 0))
2005	(label_ref (match_operand 0 "" ""))
2006	(pc)))]
2007	""
2008	"*
2009	{ if (cc_prev_status.flags & CC_Z_IN_F)
2010	return \"bfs %l0\";
2011	else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2012	return \"bfc %l0\";
2013	else return \"bne %l0\";
2014	}")
2015
2016	(define_insn "bgt"
2017	[(set (pc)
2018	(if_then_else (gt (cc0)
2019	(const_int 0))
2020	(label_ref (match_operand 0 "" ""))
2021	(pc)))]
2022	""
2023	"bgt %l0")
2024
2025	(define_insn "bgtu"
2026	[(set (pc)
2027	(if_then_else (gtu (cc0)
2028	(const_int 0))
2029	(label_ref (match_operand 0 "" ""))
2030	(pc)))]
2031	""
2032	"bhi %l0")
2033
2034	(define_insn "blt"
2035	[(set (pc)
2036	(if_then_else (lt (cc0)
2037	(const_int 0))
2038	(label_ref (match_operand 0 "" ""))
2039	(pc)))]
2040	""
2041	"blt %l0")
2042
2043	(define_insn "bltu"
2044	[(set (pc)
2045	(if_then_else (ltu (cc0)
2046	(const_int 0))
2047	(label_ref (match_operand 0 "" ""))
2048	(pc)))]
2049	""
2050	"blo %l0")
2051
2052	(define_insn "bge"
2053	[(set (pc)
2054	(if_then_else (ge (cc0)
2055	(const_int 0))
2056	(label_ref (match_operand 0 "" ""))
2057	(pc)))]
2058	""
2059	"bge %l0")
2060
2061	(define_insn "bgeu"
2062	[(set (pc)
2063	(if_then_else (geu (cc0)
2064	(const_int 0))
2065	(label_ref (match_operand 0 "" ""))
2066	(pc)))]
2067	""
2068	"bhs %l0")
2069
2070	(define_insn "ble"
2071	[(set (pc)
2072	(if_then_else (le (cc0)
2073	(const_int 0))
2074	(label_ref (match_operand 0 "" ""))
2075	(pc)))]
2076	""
2077	"ble %l0")
2078
2079	(define_insn "bleu"
2080	[(set (pc)
2081	(if_then_else (leu (cc0)
2082	(const_int 0))
2083	(label_ref (match_operand 0 "" ""))
2084	(pc)))]
2085	""
2086	"bls %l0")
2087
2088	(define_insn ""
2089	[(set (pc)
2090	(if_then_else (eq (cc0)
2091	(const_int 0))
2092	(pc)
2093	(label_ref (match_operand 0 "" ""))))]
2094	""
2095	"*
2096	{ if (cc_prev_status.flags & CC_Z_IN_F)
2097	return \"bfs %l0\";
2098	else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2099	return \"bfc %l0\";
2100	else return \"bne %l0\";
2101	}")
2102
2103	(define_insn ""
2104	[(set (pc)
2105	(if_then_else (ne (cc0)
2106	(const_int 0))
2107	(pc)
2108	(label_ref (match_operand 0 "" ""))))]
2109	""
2110	"*
2111	{ if (cc_prev_status.flags & CC_Z_IN_F)
2112	return \"bfc %l0\";
2113	else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2114	return \"bfs %l0\";
2115	else return \"beq %l0\";
2116	}")
2117
2118	(define_insn ""
2119	[(set (pc)
2120	(if_then_else (gt (cc0)
2121	(const_int 0))
2122	(pc)
2123	(label_ref (match_operand 0 "" ""))))]
2124	""
2125	"ble %l0")
2126
2127	(define_insn ""
2128	[(set (pc)
2129	(if_then_else (gtu (cc0)
2130	(const_int 0))
2131	(pc)
2132	(label_ref (match_operand 0 "" ""))))]
2133	""
2134	"bls %l0")
2135
2136	(define_insn ""
2137	[(set (pc)
2138	(if_then_else (lt (cc0)
2139	(const_int 0))
2140	(pc)
2141	(label_ref (match_operand 0 "" ""))))]
2142	""
2143	"bge %l0")
2144
2145	(define_insn ""
2146	[(set (pc)
2147	(if_then_else (ltu (cc0)
2148	(const_int 0))
2149	(pc)
2150	(label_ref (match_operand 0 "" ""))))]
2151	""
2152	"bhs %l0")
2153
2154	(define_insn ""
2155	[(set (pc)
2156	(if_then_else (ge (cc0)
2157	(const_int 0))
2158	(pc)
2159	(label_ref (match_operand 0 "" ""))))]
2160	""
2161	"blt %l0")
2162
2163	(define_insn ""
2164	[(set (pc)
2165	(if_then_else (geu (cc0)
2166	(const_int 0))
2167	(pc)
2168	(label_ref (match_operand 0 "" ""))))]
2169	""
2170	"blo %l0")
2171
2172	(define_insn ""
2173	[(set (pc)
2174	(if_then_else (le (cc0)
2175	(const_int 0))
2176	(pc)
2177	(label_ref (match_operand 0 "" ""))))]
2178	""
2179	"bgt %l0")
2180
2181	(define_insn ""
2182	[(set (pc)
2183	(if_then_else (leu (cc0)
2184	(const_int 0))
2185	(pc)
2186	(label_ref (match_operand 0 "" ""))))]
2187	""
2188	"bhi %l0")
2189
2190	;; Subtract-and-jump and Add-and-jump insns.
2191	;; These can actually be used for adding numbers in the range -8 to 7
2192
2193	(define_insn ""
2194	[(set (pc)
2195	(if_then_else
2196	(ne (match_operand:SI 0 "general_operand" "+g")
2197	(match_operand:SI 1 "const_int_operand" "i"))
2198	(label_ref (match_operand 2 "" ""))
2199	(pc)))
2200	(set (match_dup 0)
2201	(minus:SI (match_dup 0)
2202	(match_dup 1)))]
2203	"INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8"
2204	"acbd %$%n1,%0,%l2")
2205
2206	(define_insn ""
2207	[(set (pc)
2208	(if_then_else
2209	(ne (match_operand:SI 0 "general_operand" "+g")
2210	(match_operand:SI 1 "const_int_operand" "i"))
2211	(label_ref (match_operand 2 "" ""))
2212	(pc)))
2213	(set (match_dup 0)
2214	(plus:SI (match_dup 0)
2215	(match_operand:SI 3 "const_int_operand" "i")))]
2216	"INTVAL (operands[1]) == - INTVAL (operands[3])
2217	&& INTVAL (operands[3]) >= -8 && INTVAL (operands[3]) < 8"
2218	"acbd %3,%0,%l2")
2219
2220	(define_insn "call"
2221	[(call (match_operand:QI 0 "memory_operand" "m")
2222	(match_operand:QI 1 "general_operand" "g"))]
2223	""
2224	"*
2225	{
2226	#ifndef JSR_ALWAYS
2227	if (GET_CODE (operands[0]) == MEM)
2228	{
2229	rtx temp = XEXP (operands[0], 0);
2230	if (CONSTANT_ADDRESS_P (temp))
2231	{
2232	#ifdef ENCORE_ASM
2233	return \"bsr %?%0\";
2234	#else
2235	#ifdef CALL_MEMREF_IMPLICIT
2236	operands[0] = temp;
2237	return \"bsr %0\";
2238	#else
2239	#ifdef GNX_V3
2240	return \"bsr %0\";
2241	#else
2242	return \"bsr %?%a0\";
2243	#endif
2244	#endif
2245	#endif
2246	}
2247	if (GET_CODE (XEXP (operands[0], 0)) == REG)
2248	#if defined (GNX_V3) \|\| defined (CALL_MEMREF_IMPLICIT)
2249	return \"jsr %0\";
2250	#else
2251	return \"jsr %a0\";
2252	#endif
2253	}
2254	#endif /* not JSR_ALWAYS */
2255	return \"jsr %0\";
2256	}")
2257
2258	(define_insn "call_value"
2259	[(set (match_operand 0 "" "=rf")
2260	(call (match_operand:QI 1 "memory_operand" "m")
2261	(match_operand:QI 2 "general_operand" "g")))]
2262	""
2263	"*
2264	{
2265	#ifndef JSR_ALWAYS
2266	if (GET_CODE (operands[1]) == MEM)
2267	{
2268	rtx temp = XEXP (operands[1], 0);
2269	if (CONSTANT_ADDRESS_P (temp))
2270	{
2271	#ifdef ENCORE_ASM
2272	return \"bsr %?%1\";
2273	#else
2274	#ifdef CALL_MEMREF_IMPLICIT
2275	operands[1] = temp;
2276	return \"bsr %1\";
2277	#else
2278	#ifdef GNX_V3
2279	return \"bsr %1\";
2280	#else
2281	return \"bsr %?%a1\";
2282	#endif
2283	#endif
2284	#endif
2285	}
2286	if (GET_CODE (XEXP (operands[1], 0)) == REG)
2287	#if defined (GNX_V3) \|\| defined (CALL_MEMREF_IMPLICIT)
2288	return \"jsr %1\";
2289	#else
2290	return \"jsr %a1\";
2291	#endif
2292	}
2293	#endif /* not JSR_ALWAYS */
2294	return \"jsr %1\";
2295	}")
2296
2297	;; Call subroutine returning any type.
2298
2299	(define_expand "untyped_call"
2300	[(parallel [(call (match_operand 0 "" "")
2301	(const_int 0))
2302	(match_operand 1 "" "")
2303	(match_operand 2 "" "")])]
2304	""
2305	"
2306	{
2307	int i;
2308
2309	emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
2310
2311	for (i = 0; i < XVECLEN (operands[2], 0); i++)
2312	{
2313	rtx set = XVECEXP (operands[2], 0, i);
2314	emit_move_insn (SET_DEST (set), SET_SRC (set));
2315	}
2316
2317	/* The optimizer does not know that the call sets the function value
2318	registers we stored in the result block. We avoid problems by
2319	claiming that all hard registers are used and clobbered at this
2320	point. */
2321	emit_insn (gen_blockage ());
2322
2323	DONE;
2324	}")
2325
2326	;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
2327	;; all of memory. This blocks insns from being moved across this point.
2328
2329	(define_insn "blockage"
2330	[(unspec_volatile [(const_int 0)] 0)]
2331	""
2332	"")
2333
2334	(define_insn "return"
2335	[(return)]
2336	"0"
2337	"ret 0")
2338
2339	(define_insn "abssf2"
2340	[(set (match_operand:SF 0 "general_operand" "=fm<")
2341	(abs:SF (match_operand:SF 1 "general_operand" "fmF")))]
2342	"TARGET_32081"
2343	"absf %1,%0")
2344
2345	(define_insn "absdf2"
2346	[(set (match_operand:DF 0 "general_operand" "=fm<")
2347	(abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
2348	"TARGET_32081"
2349	"absl %1,%0")
2350
2351	(define_insn "abssi2"
2352	[(set (match_operand:SI 0 "general_operand" "=g<")
2353	(abs:SI (match_operand:SI 1 "general_operand" "rmn")))]
2354	""
2355	"absd %1,%0")
2356
2357	(define_insn "abshi2"
2358	[(set (match_operand:HI 0 "general_operand" "=g<")
2359	(abs:HI (match_operand:HI 1 "general_operand" "g")))]
2360	""
2361	"absw %1,%0")
2362
2363	(define_insn "absqi2"
2364	[(set (match_operand:QI 0 "general_operand" "=g<")
2365	(abs:QI (match_operand:QI 1 "general_operand" "g")))]
2366	""
2367	"absb %1,%0")
2368
2369	(define_insn "nop"
2370	[(const_int 0)]
2371	""
2372	"nop")
2373
2374	(define_insn "indirect_jump"
2375	[(set (pc) (match_operand:SI 0 "register_operand" "r"))]
2376	""
2377	"jump %0")
2378
2379	(define_insn "tablejump"
2380	[(set (pc)
2381	(plus:SI (pc) (match_operand:SI 0 "general_operand" "g")))
2382	(use (label_ref (match_operand 1 "" "")))]
2383	""
2384	"*
2385	{
2386	ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
2387	CODE_LABEL_NUMBER (operands[1]));
2388	return \"cased %0\";
2389	}")
2390
2391	;; Scondi instructions
2392	(define_insn "seq"
2393	[(set (match_operand:SI 0 "general_operand" "=g<")
2394	(eq:SI (cc0) (const_int 0)))]
2395	""
2396	"*
2397	{ if (cc_prev_status.flags & CC_Z_IN_F)
2398	return \"sfcd %0\";
2399	else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2400	return \"sfsd %0\";
2401	else return \"seqd %0\";
2402	}")
2403
2404	(define_insn ""
2405	[(set (match_operand:HI 0 "general_operand" "=g<")
2406	(eq:HI (cc0) (const_int 0)))]
2407	""
2408	"*
2409	{ if (cc_prev_status.flags & CC_Z_IN_F)
2410	return \"sfcw %0\";
2411	else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2412	return \"sfsw %0\";
2413	else return \"seqw %0\";
2414	}")
2415
2416	(define_insn ""
2417	[(set (match_operand:QI 0 "general_operand" "=g<")
2418	(eq:QI (cc0) (const_int 0)))]
2419	""
2420	"*
2421	{ if (cc_prev_status.flags & CC_Z_IN_F)
2422	return \"sfcb %0\";
2423	else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2424	return \"sfsb %0\";
2425	else return \"seqb %0\";
2426	}")
2427
2428	(define_insn "sne"
2429	[(set (match_operand:SI 0 "general_operand" "=g<")
2430	(ne:SI (cc0) (const_int 0)))]
2431	""
2432	"*
2433	{ if (cc_prev_status.flags & CC_Z_IN_F)
2434	return \"sfsd %0\";
2435	else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2436	return \"sfcd %0\";
2437	else return \"sned %0\";
2438	}")
2439
2440	(define_insn ""
2441	[(set (match_operand:HI 0 "general_operand" "=g<")
2442	(ne:HI (cc0) (const_int 0)))]
2443	""
2444	"*
2445	{ if (cc_prev_status.flags & CC_Z_IN_F)
2446	return \"sfsw %0\";
2447	else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2448	return \"sfcw %0\";
2449	else return \"snew %0\";
2450	}")
2451
2452	(define_insn ""
2453	[(set (match_operand:QI 0 "general_operand" "=g<")
2454	(ne:QI (cc0) (const_int 0)))]
2455	""
2456	"*
2457	{ if (cc_prev_status.flags & CC_Z_IN_F)
2458	return \"sfsb %0\";
2459	else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2460	return \"sfcb %0\";
2461	else return \"sneb %0\";
2462	}")
2463
2464	(define_insn "sgt"
2465	[(set (match_operand:SI 0 "general_operand" "=g<")
2466	(gt:SI (cc0) (const_int 0)))]
2467	""
2468	"sgtd %0")
2469
2470	(define_insn ""
2471	[(set (match_operand:HI 0 "general_operand" "=g<")
2472	(gt:HI (cc0) (const_int 0)))]
2473	""
2474	"sgtw %0")
2475
2476	(define_insn ""
2477	[(set (match_operand:QI 0 "general_operand" "=g<")
2478	(gt:QI (cc0) (const_int 0)))]
2479	""
2480	"sgtb %0")
2481
2482	(define_insn "sgtu"
2483	[(set (match_operand:SI 0 "general_operand" "=g<")
2484	(gtu:SI (cc0) (const_int 0)))]
2485	""
2486	"shid %0")
2487
2488	(define_insn ""
2489	[(set (match_operand:HI 0 "general_operand" "=g<")
2490	(gtu:HI (cc0) (const_int 0)))]
2491	""
2492	"shiw %0")
2493
2494	(define_insn ""
2495	[(set (match_operand:QI 0 "general_operand" "=g<")
2496	(gtu:QI (cc0) (const_int 0)))]
2497	""
2498	"shib %0")
2499
2500	(define_insn "slt"
2501	[(set (match_operand:SI 0 "general_operand" "=g<")
2502	(lt:SI (cc0) (const_int 0)))]
2503	""
2504	"sltd %0")
2505
2506	(define_insn ""
2507	[(set (match_operand:HI 0 "general_operand" "=g<")
2508	(lt:HI (cc0) (const_int 0)))]
2509	""
2510	"sltw %0")
2511
2512	(define_insn ""
2513	[(set (match_operand:QI 0 "general_operand" "=g<")
2514	(lt:QI (cc0) (const_int 0)))]
2515	""
2516	"sltb %0")
2517
2518	(define_insn "sltu"
2519	[(set (match_operand:SI 0 "general_operand" "=g<")
2520	(ltu:SI (cc0) (const_int 0)))]
2521	""
2522	"slod %0")
2523
2524	(define_insn ""
2525	[(set (match_operand:HI 0 "general_operand" "=g<")
2526	(ltu:HI (cc0) (const_int 0)))]
2527	""
2528	"slow %0")
2529
2530	(define_insn ""
2531	[(set (match_operand:QI 0 "general_operand" "=g<")
2532	(ltu:QI (cc0) (const_int 0)))]
2533	""
2534	"slob %0")
2535
2536	(define_insn "sge"
2537	[(set (match_operand:SI 0 "general_operand" "=g<")
2538	(ge:SI (cc0) (const_int 0)))]
2539	""
2540	"sged %0")
2541
2542	(define_insn ""
2543	[(set (match_operand:HI 0 "general_operand" "=g<")
2544	(ge:HI (cc0) (const_int 0)))]
2545	""
2546	"sgew %0")
2547
2548	(define_insn ""
2549	[(set (match_operand:QI 0 "general_operand" "=g<")
2550	(ge:QI (cc0) (const_int 0)))]
2551	""
2552	"sgeb %0")
2553
2554	(define_insn "sgeu"
2555	[(set (match_operand:SI 0 "general_operand" "=g<")
2556	(geu:SI (cc0) (const_int 0)))]
2557	""
2558	"shsd %0")
2559
2560	(define_insn ""
2561	[(set (match_operand:HI 0 "general_operand" "=g<")
2562	(geu:HI (cc0) (const_int 0)))]
2563	""
2564	"shsw %0")
2565
2566	(define_insn ""
2567	[(set (match_operand:QI 0 "general_operand" "=g<")
2568	(geu:QI (cc0) (const_int 0)))]
2569	""
2570	"shsb %0")
2571
2572	(define_insn "sle"
2573	[(set (match_operand:SI 0 "general_operand" "=g<")
2574	(le:SI (cc0) (const_int 0)))]
2575	""
2576	"sled %0")
2577
2578	(define_insn ""
2579	[(set (match_operand:HI 0 "general_operand" "=g<")
2580	(le:HI (cc0) (const_int 0)))]
2581	""
2582	"slew %0")
2583
2584	(define_insn ""
2585	[(set (match_operand:QI 0 "general_operand" "=g<")
2586	(le:QI (cc0) (const_int 0)))]
2587	""
2588	"sleb %0")
2589
2590	(define_insn "sleu"
2591	[(set (match_operand:SI 0 "general_operand" "=g<")
2592	(leu:SI (cc0) (const_int 0)))]
2593	""
2594	"slsd %0")
2595
2596	(define_insn ""
2597	[(set (match_operand:HI 0 "general_operand" "=g<")
2598	(leu:HI (cc0) (const_int 0)))]
2599	""
2600	"slsw %0")
2601
2602	(define_insn ""
2603	[(set (match_operand:QI 0 "general_operand" "=g<")
2604	(leu:QI (cc0) (const_int 0)))]
2605	""
2606	"slsb %0")
2607
2608	;; ffs instructions
2609
2610	(define_insn "ffsqi2"
2611	[(set (match_operand:QI 0 "general_operand" "=g")
2612	(ffs:QI (match_operand:SI 1 "general_operand" "g")))]
2613	""
2614	"*
2615	{
2616	return \"movqb 0,%0; ffsd %1,%0; bfs 1f; addqb 1,%0; 1:\";
2617	}")
2618
2619	(define_insn "ffshi2"
2620	[(set (match_operand:HI 0 "general_operand" "=g")
2621	(ffs:HI (match_operand:SI 1 "general_operand" "g")))]
2622	""
2623	"*
2624	{
2625	return \"movqw 0,%0; ffsd %1,%0; bfs 1f; addqw 1,%0; 1:\";
2626	}")
2627
2628	(define_insn "ffssi2"
2629	[(set (match_operand:SI 0 "general_operand" "=g")
2630	(ffs:SI (match_operand:SI 1 "general_operand" "g")))]
2631	""
2632	"*
2633	{
2634	return \"movqd 0,%0; ffsd %1,%0; bfs 1f; addqd 1,%0; 1:\";
2635	}")
2636
2637	;; Speed up stack adjust followed by a HI fixedpoint push.
2638
2639	(define_peephole
2640	[(set (reg:SI 17) (plus:SI (reg:SI 17) (const_int -2)))
2641	(set (match_operand:HI 0 "push_operand" "=m")
2642	(match_operand:HI 1 "general_operand" "g"))]
2643	"! reg_mentioned_p (stack_pointer_rtx, operands[1])"
2644	"*
2645	{
2646	if (GET_CODE (operands[1]) == CONST_INT)
2647	output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%$%1,tos\"),
2648	operands);
2649	else
2650	output_asm_insn (\"movzwd %1,tos\", operands);
2651	return \"\";
2652	}")
2653
2654	;; Speed up stack adjust followed by a zero_extend:HI(QI) fixedpoint push.
2655
2656	(define_peephole
2657	[(set (reg:SI 17) (plus:SI (reg:SI 17) (const_int -2)))
2658	(set (match_operand:HI 0 "push_operand" "=m")
2659	(zero_extend:HI (match_operand:QI 1 "general_operand" "g")))]
2660	"! reg_mentioned_p (stack_pointer_rtx, operands[1])"
2661	"*
2662	{
2663	if (GET_CODE (operands[1]) == CONST_INT)
2664	output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%$%1,tos\"),
2665	operands);
2666	else
2667	output_asm_insn (\"movzbd %1,tos\", operands);
2668	return \"\";
2669	}")
2670
2671	;; Speed up stack adjust followed by a sign_extend:HI(QI) fixedpoint push.
2672
2673	(define_peephole
2674	[(set (reg:SI 17) (plus:SI (reg:SI 17) (const_int -2)))
2675	(set (match_operand:HI 0 "push_operand" "=m")
2676	(sign_extend:HI (match_operand:QI 1 "general_operand" "g")))]
2677	"! reg_mentioned_p (stack_pointer_rtx, operands[1])"
2678	"*
2679	{
2680	if (GET_CODE (operands[1]) == CONST_INT)
2681	output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%$%1,tos\"),
2682	operands);
2683	else
2684	output_asm_insn (\"movxbd %1,tos\", operands);
2685	return \"\";
2686	}")
2687
2688	;; Speed up stack adjust followed by a QI fixedpoint push.
2689
2690	(define_peephole
2691	[(set (reg:SI 17) (plus:SI (reg:SI 17) (const_int -3)))
2692	(set (match_operand:QI 0 "push_operand" "=m")
2693	(match_operand:QI 1 "general_operand" "g"))]
2694	"! reg_mentioned_p (stack_pointer_rtx, operands[1])"
2695	"*
2696	{
2697	if (GET_CODE (operands[1]) == CONST_INT)
2698	output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%$%1,tos\"),
2699	operands);
2700	else
2701	output_asm_insn (\"movzbd %1,tos\", operands);
2702	return \"\";
2703	}")
2704
2705	;; Speed up stack adjust followed by a SI fixedpoint push.
2706
2707	(define_peephole
2708	[(set (reg:SI 17) (plus:SI (reg:SI 17) (const_int 4)))
2709	(set (match_operand:SI 0 "push_operand" "=m")
2710	(match_operand:SI 1 "general_operand" "g"))]
2711	"! reg_mentioned_p (stack_pointer_rtx, operands[1])"
2712	"*
2713	{
2714	if (GET_CODE (operands[1]) == CONST_INT)
2715	output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%$%1,0(sp)\"),
2716	operands);
2717	else if (GET_CODE (operands[1]) != REG
2718	&& GET_CODE (operands[1]) != MEM
2719	&& address_operand (operands[1], SImode))
2720	output_asm_insn (\"addr %a1,0(sp)\", operands);
2721	else
2722	output_asm_insn (\"movd %1,0(sp)\", operands);
2723	return \"\";
2724	}")
2725
2726	;; Speed up stack adjust followed by two fullword fixedpoint pushes.
2727
2728	(define_peephole
2729	[(set (reg:SI 17) (plus:SI (reg:SI 17) (const_int 8)))
2730	(set (match_operand:SI 0 "push_operand" "=m")
2731	(match_operand:SI 1 "general_operand" "g"))
2732	(set (match_operand:SI 2 "push_operand" "=m")
2733	(match_operand:SI 3 "general_operand" "g"))]
2734	"! reg_mentioned_p (stack_pointer_rtx, operands[1])
2735	&& ! reg_mentioned_p (stack_pointer_rtx, operands[3])"
2736	"*
2737	{
2738	if (GET_CODE (operands[1]) == CONST_INT)
2739	output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%$%1,4(sp)\"),
2740	operands);
2741	else if (GET_CODE (operands[1]) != REG
2742	&& GET_CODE (operands[1]) != MEM
2743	&& address_operand (operands[1], SImode))
2744	output_asm_insn (\"addr %a1,4(sp)\", operands);
2745	else
2746	output_asm_insn (\"movd %1,4(sp)\", operands);
2747
2748	if (GET_CODE (operands[3]) == CONST_INT)
2749	output_asm_insn (output_move_dconst (INTVAL (operands[3]), \"%$%3,0(sp)\"),
2750	operands);
2751	else if (GET_CODE (operands[3]) != REG
2752	&& GET_CODE (operands[3]) != MEM
2753	&& address_operand (operands[3], SImode))
2754	output_asm_insn (\"addr %a3,0(sp)\", operands);
2755	else
2756	output_asm_insn (\"movd %3,0(sp)\", operands);
2757	return \"\";
2758	}")

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