1 | ;;- Machine description for the Hitachi SH. |
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2 | ;; Copyright (C) 1993, 1994, 1995 Free Software Foundation, Inc. |
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3 | ;; Contributed by Steve Chamberlain (sac@cygnus.com). |
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4 | ;; Improved by Jim Wilson (wilson@cygnus.com). |
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5 | |
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6 | ;; This file is part of GNU CC. |
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7 | |
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8 | ;; GNU CC is free software; you can redistribute it and/or modify |
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9 | ;; it under the terms of the GNU General Public License as published by |
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10 | ;; the Free Software Foundation; either version 2, or (at your option) |
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11 | ;; any later version. |
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12 | |
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13 | ;; GNU CC is distributed in the hope that it will be useful, |
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14 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of |
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15 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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16 | ;; GNU General Public License for more details. |
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17 | |
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18 | ;; You should have received a copy of the GNU General Public License |
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19 | ;; along with GNU CC; see the file COPYING. If not, write to |
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20 | ;; the Free Software Foundation, 59 Temple Place - Suite 330, |
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21 | ;; Boston, MA 02111-1307, USA. |
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22 | |
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23 | |
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24 | ;; ??? Should prepend a * to all pattern names which are not used. |
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25 | ;; This will make the compiler smaller, and rebuilds after changes faster. |
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26 | |
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27 | ;; ??? Should be enhanced to include support for many more GNU superoptimizer |
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28 | ;; sequences. Especially the sequences for arithmetic right shifts. |
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29 | |
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30 | ;; ??? Should check all DImode patterns for consistency and usefulness. |
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31 | |
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32 | ;; ??? Should add support for using BSR for short function calls. |
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33 | |
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34 | ;; ??? The MAC.W and MAC.L instructions are not supported. There is no |
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35 | ;; way to generate them. |
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36 | |
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37 | ;; ??? The BSR instruction is not supported. It might be possible to |
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38 | ;; generate it by keeping track of function sizes (and hence relative |
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39 | ;; addresses), and then using it only if the target is earlier in the same |
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40 | ;; file, and is within range. Better would be assembler/linker relaxing, |
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41 | ;; but that is much harder. |
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42 | |
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43 | ;; ??? The cmp/str instruction is not supported. Perhaps it can be used |
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44 | ;; for a str* inline function. |
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45 | |
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46 | ;; Special constraints for SH machine description: |
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47 | ;; |
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48 | ;; t -- T |
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49 | ;; x -- mac |
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50 | ;; l -- pr |
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51 | ;; z -- r0 |
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52 | ;; |
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53 | ;; Special formats used for outputting SH instructions: |
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54 | ;; |
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55 | ;; %. -- print a .s if insn needs delay slot |
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56 | ;; %@ -- print rte/rts if is/isn't an interrupt function |
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57 | ;; %# -- output a nop if there is nothing to put in the delay slot |
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58 | ;; %O -- print a constant without the # |
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59 | ;; %R -- print the lsw reg of a double |
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60 | ;; %S -- print the msw reg of a double |
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61 | ;; %T -- print next word of a double REG or MEM |
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62 | ;; |
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63 | ;; Special predicates: |
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64 | ;; |
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65 | ;; arith_operand -- operand is valid source for arithmetic op |
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66 | ;; arith_reg_operand -- operand is valid register for arithmetic op |
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67 | ;; general_movdst_operand -- operand is valid move destination |
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68 | ;; general_movsrc_operand -- operand is valid move source |
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69 | ;; logical_operand -- operand is valid source for logical op |
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70 | ;; ------------------------------------------------------------------------- |
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71 | ;; Attributes |
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72 | ;; ------------------------------------------------------------------------- |
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73 | |
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74 | ; Target CPU. |
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75 | |
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76 | (define_attr "cpu" "sh0,sh1,sh2,sh3" |
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77 | (const (symbol_ref "sh_cpu_attr"))) |
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78 | |
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79 | ;; |
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80 | ;; cbranch conditional branch instructions |
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81 | ;; jump unconditional jumps |
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82 | ;; arith ordinary arithmetic |
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83 | ;; load from memory |
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84 | ;; store to memory |
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85 | ;; move register to register |
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86 | ;; smpy word precision integer multiply |
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87 | ;; dmpy longword or doublelongword precision integer multiply |
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88 | ;; return rts |
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89 | ;; pload load of pr reg, which can't be put into delay slot of rts |
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90 | ;; pstore store of pr reg, which can't be put into delay slot of jsr |
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91 | ;; pcload pc relative load of constant value |
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92 | ;; rte return from exception |
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93 | ;; sfunc special function call with known used registers |
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94 | ;; call function call |
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95 | |
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96 | (define_attr "type" |
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97 | "cbranch,jump,arith,other,load,store,move,smpy,dmpy,return,pload,pstore,pcload,rte,sfunc,call" |
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98 | (const_string "other")) |
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99 | |
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100 | ; If a conditional branch destination is within -252..258 bytes away |
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101 | ; from the instruction it can be 2 bytes long. Something in the |
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102 | ; range -4090..4100 bytes can be 6 bytes long. All other conditional |
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103 | ; branches are 16 bytes long. |
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104 | |
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105 | ; An unconditional jump in the range -4092..4098 can be 2 bytes long. |
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106 | ; Otherwise, it must be 14 bytes long. |
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107 | |
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108 | ; All other instructions are two bytes long by default. |
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109 | |
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110 | ; All positive offsets have an adjustment added, which is the number of bytes |
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111 | ; difference between this instruction length and the next larger instruction |
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112 | ; length. This is because shorten_branches starts with the largest |
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113 | ; instruction size and then tries to reduce them. |
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114 | |
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115 | (define_attr "length" "" |
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116 | (cond [(eq_attr "type" "cbranch") |
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117 | (if_then_else (and (ge (minus (match_dup 0) (pc)) |
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118 | (const_int -252)) |
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119 | (le (minus (match_dup 0) (pc)) |
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120 | (const_int 262))) |
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121 | (const_int 2) |
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122 | (if_then_else (and (ge (minus (match_dup 0) (pc)) |
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123 | (const_int -4090)) |
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124 | (le (minus (match_dup 0) (pc)) |
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125 | (const_int 4110))) |
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126 | (const_int 6) |
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127 | (const_int 16))) |
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128 | |
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129 | (eq_attr "type" "jump") |
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130 | (if_then_else (and (ge (minus (match_dup 0) (pc)) |
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131 | (const_int -4092)) |
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132 | (le (minus (match_dup 0) (pc)) |
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133 | (const_int 4110))) |
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134 | (const_int 2) |
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135 | (const_int 14)) |
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136 | ] (const_int 2))) |
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137 | |
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138 | ;; (define_function_unit {name} {num-units} {n-users} {test} |
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139 | ;; {ready-delay} {issue-delay} [{conflict-list}]) |
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140 | |
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141 | ;; ??? These are probably not correct. |
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142 | (define_function_unit "memory" 1 0 (eq_attr "type" "load,pcload,pload") 2 2) |
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143 | (define_function_unit "mpy" 1 0 (eq_attr "type" "smpy") 2 2) |
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144 | (define_function_unit "mpy" 1 0 (eq_attr "type" "dmpy") 3 3) |
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145 | |
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146 | ; Definitions for filling branch delay slots. |
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147 | |
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148 | (define_attr "needs_delay_slot" "yes,no" (const_string "no")) |
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149 | |
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150 | (define_attr "hit_stack" "yes,no" (const_string "no")) |
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151 | |
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152 | (define_attr "interrupt_function" "no,yes" |
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153 | (const (symbol_ref "pragma_interrupt"))) |
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154 | |
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155 | (define_attr "in_delay_slot" "yes,no" |
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156 | (cond [(eq_attr "type" "cbranch") (const_string "no") |
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157 | (eq_attr "type" "pcload") (const_string "no") |
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158 | (eq_attr "needs_delay_slot" "yes") (const_string "no") |
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159 | (eq_attr "length" "2") (const_string "yes") |
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160 | ] (const_string "no"))) |
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161 | |
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162 | (define_delay |
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163 | (eq_attr "needs_delay_slot" "yes") |
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164 | [(eq_attr "in_delay_slot" "yes") (nil) (nil)]) |
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165 | |
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166 | ;; On the SH and SH2, the rte instruction reads the return pc from the stack, |
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167 | ;; and thus we can't put a pop instruction in its delay slot. |
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168 | ;; ??? On the SH3, the rte instruction does not use the stack, so a pop |
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169 | ;; instruction can go in the delay slot. |
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170 | |
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171 | ;; Since a normal return (rts) implicitly uses the PR register, |
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172 | ;; we can't allow PR register loads in an rts delay slot. |
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173 | |
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174 | (define_delay |
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175 | (eq_attr "type" "return") |
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176 | [(and (eq_attr "in_delay_slot" "yes") |
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177 | (ior (and (eq_attr "interrupt_function" "no") |
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178 | (eq_attr "type" "!pload")) |
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179 | (and (eq_attr "interrupt_function" "yes") |
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180 | (eq_attr "hit_stack" "no")))) (nil) (nil)]) |
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181 | |
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182 | ;; Since a call implicitly uses the PR register, we can't allow |
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183 | ;; a PR register store in a jsr delay slot. |
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184 | |
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185 | (define_delay |
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186 | (ior (eq_attr "type" "call") (eq_attr "type" "sfunc")) |
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187 | [(and (eq_attr "in_delay_slot" "yes") |
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188 | (eq_attr "type" "!pstore")) (nil) (nil)]) |
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189 | |
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190 | ;; Say that we have annulled true branches, since this gives smaller and |
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191 | ;; faster code when branches are predicted as not taken. |
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192 | |
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193 | ;; ??? Branches which are out-of-range actually have two delay slots, |
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194 | ;; the first is either always executed or else annulled false, and the |
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195 | ;; second is always annulled false. Handling these differently from |
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196 | ;; in range branches would give better code. |
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197 | |
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198 | (define_delay |
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199 | (and (eq_attr "type" "cbranch") |
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200 | (eq_attr "cpu" "sh2,sh3")) |
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201 | [(eq_attr "in_delay_slot" "yes") (eq_attr "in_delay_slot" "yes") (nil)]) |
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202 | |
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203 | ;; ------------------------------------------------------------------------- |
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204 | ;; SImode signed integer comparisons |
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205 | ;; ------------------------------------------------------------------------- |
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206 | |
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207 | (define_insn "" |
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208 | [(set (match_operand:SI 0 "arith_reg_operand" "=r") |
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209 | (eq:SI (reg:SI 18) |
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210 | (const_int 1)))] |
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211 | "" |
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212 | "movt %0") |
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213 | |
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214 | ;; ??? This combiner pattern does not work, because combine does not combine |
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215 | ;; instructions that set a hard register when SMALL_REGISTER_CLASSES is |
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216 | ;; defined. Perhaps use a pseudo-reg for the T bit? |
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217 | |
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218 | (define_insn "" |
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219 | [(set (reg:SI 18) |
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220 | (eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "z,r") |
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221 | (match_operand:SI 1 "arith_operand" "L,r")) |
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222 | (const_int 0)))] |
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223 | "" |
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224 | "tst %1,%0") |
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225 | |
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226 | ;; ??? Perhaps should only accept reg/constant if the register is reg 0. |
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227 | ;; That would still allow reload to create cmpi instructions, but would |
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228 | ;; perhaps allow forcing the constant into a register when that is better. |
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229 | ;; Probably should use r0 for mem/imm compares, but force constant into a |
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230 | ;; register for pseudo/imm compares. |
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231 | |
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232 | (define_insn "cmpeqsi_t" |
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233 | [(set (reg:SI 18) (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r") |
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234 | (match_operand:SI 1 "arith_operand" "N,rI,r")))] |
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235 | "" |
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236 | "@ |
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237 | tst %0,%0 |
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238 | cmp/eq %1,%0 |
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239 | cmp/eq %1,%0") |
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240 | |
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241 | (define_insn "cmpgtsi_t" |
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242 | [(set (reg:SI 18) (gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r") |
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243 | (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))] |
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244 | "" |
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245 | "@ |
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246 | cmp/gt %1,%0 |
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247 | cmp/pl %0") |
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248 | |
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249 | (define_insn "cmpgesi_t" |
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250 | [(set (reg:SI 18) (ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r") |
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251 | (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))] |
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252 | "" |
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253 | "@ |
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254 | cmp/ge %1,%0 |
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255 | cmp/pz %0") |
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256 | |
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257 | ;; ------------------------------------------------------------------------- |
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258 | ;; SImode unsigned integer comparisons |
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259 | ;; ------------------------------------------------------------------------- |
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260 | |
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261 | (define_insn "cmpgeusi_t" |
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262 | [(set (reg:SI 18) (geu:SI (match_operand:SI 0 "arith_reg_operand" "r") |
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263 | (match_operand:SI 1 "arith_reg_operand" "r")))] |
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264 | "" |
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265 | "cmp/hs %1,%0") |
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266 | |
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267 | (define_insn "cmpgtusi_t" |
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268 | [(set (reg:SI 18) (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r") |
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269 | (match_operand:SI 1 "arith_reg_operand" "r")))] |
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270 | "" |
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271 | "cmp/hi %1,%0") |
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272 | |
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273 | ;; We save the compare operands in the cmpxx patterns and use them when |
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274 | ;; we generate the branch. |
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275 | |
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276 | (define_expand "cmpsi" |
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277 | [(set (reg:SI 18) (compare (match_operand:SI 0 "arith_operand" "") |
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278 | (match_operand:SI 1 "arith_operand" "")))] |
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279 | "" |
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280 | " |
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281 | { |
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282 | sh_compare_op0 = operands[0]; |
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283 | sh_compare_op1 = operands[1]; |
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284 | DONE; |
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285 | }") |
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286 | |
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287 | ;; ------------------------------------------------------------------------- |
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288 | ;; Addition instructions |
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289 | ;; ------------------------------------------------------------------------- |
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290 | |
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291 | ;; ??? This should be a define expand. |
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292 | |
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293 | (define_insn "adddi3" |
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294 | [(set (match_operand:DI 0 "arith_reg_operand" "=r") |
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295 | (plus:DI (match_operand:DI 1 "arith_reg_operand" "%0") |
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296 | (match_operand:DI 2 "arith_reg_operand" "r"))) |
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297 | (clobber (reg:SI 18))] |
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298 | "" |
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299 | "clrt\;addc %R2,%R0\;addc %S2,%S0" |
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300 | [(set_attr "length" "6")]) |
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301 | |
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302 | (define_insn "addsi3" |
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303 | [(set (match_operand:SI 0 "arith_reg_operand" "=r") |
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304 | (plus:SI (match_operand:SI 1 "arith_operand" "%0") |
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305 | (match_operand:SI 2 "arith_operand" "rI")))] |
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306 | "" |
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307 | "add %2,%0" |
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308 | [(set_attr "type" "arith")]) |
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309 | |
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310 | ;; ------------------------------------------------------------------------- |
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311 | ;; Subtraction instructions |
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312 | ;; ------------------------------------------------------------------------- |
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313 | |
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314 | ;; ??? This should be a define expand. |
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315 | |
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316 | (define_insn "subdi3" |
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317 | [(set (match_operand:DI 0 "arith_reg_operand" "=r") |
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318 | (minus:DI (match_operand:DI 1 "arith_reg_operand" "0") |
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319 | (match_operand:DI 2 "arith_reg_operand" "r"))) |
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320 | (clobber (reg:SI 18))] |
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321 | "" |
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322 | "clrt\;subc %R2,%R0\;subc %S2,%S0" |
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323 | [(set_attr "length" "6")]) |
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324 | |
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325 | (define_insn "subsi3" |
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326 | [(set (match_operand:SI 0 "arith_reg_operand" "=r") |
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327 | (minus:SI (match_operand:SI 1 "arith_reg_operand" "0") |
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328 | (match_operand:SI 2 "arith_reg_operand" "r")))] |
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329 | "" |
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330 | "sub %2,%0" |
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331 | [(set_attr "type" "arith")]) |
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332 | |
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333 | ;; ------------------------------------------------------------------------- |
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334 | ;; Division instructions |
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335 | ;; ------------------------------------------------------------------------- |
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336 | |
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337 | ;; We take advantage of the library routines which don't clobber as many |
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338 | ;; registers as a normal function call would. |
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339 | |
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340 | ;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than |
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341 | ;; hard register 0. If we used hard register 0, then the next instruction |
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342 | ;; would be a move from hard register 0 to a pseudo-reg. If the pseudo-reg |
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343 | ;; gets allocated to a stack slot that needs its address reloaded, then |
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344 | ;; there is nothing to prevent reload from using r0 to reload the address. |
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345 | ;; This reload would clobber the value in r0 we are trying to store. |
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346 | ;; If we let reload allocate r0, then this problem can never happen. |
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347 | |
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348 | (define_insn "" |
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349 | [(set (match_operand:SI 1 "register_operand" "=z") |
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350 | (udiv:SI (reg:SI 4) (reg:SI 5))) |
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351 | (clobber (reg:SI 18)) |
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352 | (clobber (reg:SI 17)) |
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353 | (clobber (reg:SI 4)) |
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354 | (use (match_operand:SI 0 "arith_reg_operand" "r"))] |
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355 | "" |
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356 | "jsr @%0%#" |
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357 | [(set_attr "type" "sfunc") |
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358 | (set_attr "needs_delay_slot" "yes")]) |
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359 | |
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360 | (define_expand "udivsi3" |
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361 | [(set (reg:SI 4) (match_operand:SI 1 "general_operand" "")) |
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362 | (set (reg:SI 5) (match_operand:SI 2 "general_operand" "")) |
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363 | (set (match_dup 3) (symbol_ref:SI "__udivsi3")) |
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364 | (parallel [(set (match_operand:SI 0 "register_operand" "") |
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365 | (udiv:SI (reg:SI 4) |
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366 | (reg:SI 5))) |
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367 | (clobber (reg:SI 18)) |
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368 | (clobber (reg:SI 17)) |
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369 | (clobber (reg:SI 4)) |
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370 | (use (match_dup 3))])] |
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371 | "" |
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372 | "operands[3] = gen_reg_rtx(SImode);") |
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373 | |
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374 | (define_insn "" |
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375 | [(set (match_operand:SI 1 "register_operand" "=z") |
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376 | (div:SI (reg:SI 4) (reg:SI 5))) |
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377 | (clobber (reg:SI 18)) |
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378 | (clobber (reg:SI 17)) |
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379 | (clobber (reg:SI 1)) |
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380 | (clobber (reg:SI 2)) |
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381 | (clobber (reg:SI 3)) |
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382 | (use (match_operand:SI 0 "arith_reg_operand" "r"))] |
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383 | "" |
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384 | "jsr @%0%#" |
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385 | [(set_attr "type" "sfunc") |
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386 | (set_attr "needs_delay_slot" "yes")]) |
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387 | |
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388 | (define_expand "divsi3" |
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389 | [(set (reg:SI 4) (match_operand:SI 1 "general_operand" "")) |
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390 | (set (reg:SI 5) (match_operand:SI 2 "general_operand" "")) |
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391 | (set (match_dup 3) (symbol_ref:SI "__sdivsi3")) |
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392 | (parallel [(set (match_operand:SI 0 "register_operand" "") |
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393 | (div:SI (reg:SI 4) |
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394 | (reg:SI 5))) |
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395 | (clobber (reg:SI 18)) |
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396 | (clobber (reg:SI 17)) |
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397 | (clobber (reg:SI 1)) |
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398 | (clobber (reg:SI 2)) |
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399 | (clobber (reg:SI 3)) |
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400 | (use (match_dup 3))])] |
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401 | "" |
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402 | "operands[3] = gen_reg_rtx(SImode);") |
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403 | |
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404 | ;; ------------------------------------------------------------------------- |
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405 | ;; Multiplication instructions |
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406 | ;; ------------------------------------------------------------------------- |
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407 | |
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408 | (define_insn "" |
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409 | [(set (reg:SI 21) |
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410 | (mult:SI (zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r")) |
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411 | (zero_extend:SI (match_operand:HI 2 "arith_reg_operand" "r"))))] |
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412 | "" |
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413 | "mulu %2,%1" |
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414 | [(set_attr "type" "smpy")]) |
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415 | |
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416 | (define_insn "" |
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417 | [(set (reg:SI 21) |
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418 | (mult:SI (sign_extend:SI |
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419 | (match_operand:HI 1 "arith_reg_operand" "r")) |
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420 | (sign_extend:SI |
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421 | (match_operand:HI 2 "arith_reg_operand" "r"))))] |
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422 | "" |
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423 | "muls %2,%1" |
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424 | [(set_attr "type" "smpy")]) |
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425 | |
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426 | (define_expand "mulhisi3" |
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427 | [(set (reg:SI 21) |
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428 | (mult:SI (sign_extend:SI |
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429 | (match_operand:HI 1 "arith_reg_operand" "")) |
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430 | (sign_extend:SI |
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431 | (match_operand:HI 2 "arith_reg_operand" "")))) |
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432 | (set (match_operand:SI 0 "arith_reg_operand" "") |
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433 | (reg:SI 21))] |
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434 | "" |
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435 | "") |
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436 | |
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437 | (define_expand "umulhisi3" |
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438 | [(set (reg:SI 21) |
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439 | (mult:SI (zero_extend:SI |
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440 | (match_operand:HI 1 "arith_reg_operand" "")) |
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441 | (zero_extend:SI |
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442 | (match_operand:HI 2 "arith_reg_operand" "")))) |
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443 | (set (match_operand:SI 0 "arith_reg_operand" "") |
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444 | (reg:SI 21))] |
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445 | "" |
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446 | "") |
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447 | |
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448 | ;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate |
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449 | ;; a call to a routine which clobbers known registers. |
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450 | |
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451 | (define_insn "" |
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452 | [(set (match_operand:SI 1 "register_operand" "=z") |
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453 | (mult:SI (reg:SI 4) (reg:SI 5))) |
---|
454 | (clobber (reg:SI 21)) |
---|
455 | (clobber (reg:SI 18)) |
---|
456 | (clobber (reg:SI 17)) |
---|
457 | (clobber (reg:SI 3)) |
---|
458 | (clobber (reg:SI 2)) |
---|
459 | (clobber (reg:SI 1)) |
---|
460 | (use (match_operand:SI 0 "arith_reg_operand" "r"))] |
---|
461 | "" |
---|
462 | "jsr @%0%#" |
---|
463 | [(set_attr "type" "sfunc") |
---|
464 | (set_attr "needs_delay_slot" "yes")]) |
---|
465 | |
---|
466 | (define_expand "mulsi3_call" |
---|
467 | [(set (reg:SI 4) (match_operand:SI 1 "general_operand" "")) |
---|
468 | (set (reg:SI 5) (match_operand:SI 2 "general_operand" "")) |
---|
469 | (set (match_dup 3) (symbol_ref:SI "__mulsi3")) |
---|
470 | (parallel[(set (match_operand:SI 0 "register_operand" "") |
---|
471 | (mult:SI (reg:SI 4) |
---|
472 | (reg:SI 5))) |
---|
473 | (clobber (reg:SI 21)) |
---|
474 | (clobber (reg:SI 18)) |
---|
475 | (clobber (reg:SI 17)) |
---|
476 | (clobber (reg:SI 3)) |
---|
477 | (clobber (reg:SI 2)) |
---|
478 | (clobber (reg:SI 1)) |
---|
479 | (use (match_dup 3))])] |
---|
480 | "" |
---|
481 | "operands[3] = gen_reg_rtx(SImode);") |
---|
482 | |
---|
483 | (define_insn "mul_l" |
---|
484 | [(set (reg:SI 21) |
---|
485 | (mult:SI (match_operand:SI 0 "arith_reg_operand" "r") |
---|
486 | (match_operand:SI 1 "arith_reg_operand" "r")))] |
---|
487 | "TARGET_SH2" |
---|
488 | "mul.l %1,%0" |
---|
489 | [(set_attr "type" "dmpy")]) |
---|
490 | |
---|
491 | (define_expand "mulsi3" |
---|
492 | [(set (reg:SI 21) |
---|
493 | (mult:SI (match_operand:SI 1 "arith_reg_operand" "") |
---|
494 | (match_operand:SI 2 "arith_reg_operand" ""))) |
---|
495 | (set (match_operand:SI 0 "arith_reg_operand" "") |
---|
496 | (reg:SI 21))] |
---|
497 | "" |
---|
498 | " |
---|
499 | { |
---|
500 | if (!TARGET_SH2) |
---|
501 | { |
---|
502 | FAIL; |
---|
503 | /* ??? Does this give worse or better code? */ |
---|
504 | emit_insn (gen_mulsi3_call (operands[0], operands[1], operands[2])); |
---|
505 | DONE; |
---|
506 | } |
---|
507 | }") |
---|
508 | |
---|
509 | (define_insn "" |
---|
510 | [(set (reg:DI 20) |
---|
511 | (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")) |
---|
512 | (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))] |
---|
513 | "TARGET_SH2" |
---|
514 | "dmuls.l %2,%1" |
---|
515 | [(set_attr "type" "dmpy")]) |
---|
516 | |
---|
517 | (define_expand "mulsidi3" |
---|
518 | [(set (reg:DI 20) |
---|
519 | (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "")) |
---|
520 | (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))) |
---|
521 | (set (match_operand:DI 0 "arith_reg_operand" "") |
---|
522 | (reg:DI 20))] |
---|
523 | "TARGET_SH2" |
---|
524 | "") |
---|
525 | |
---|
526 | (define_insn "" |
---|
527 | [(set (reg:DI 20) |
---|
528 | (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")) |
---|
529 | (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))] |
---|
530 | "TARGET_SH2" |
---|
531 | "dmulu.l %2,%1" |
---|
532 | [(set_attr "type" "dmpy")]) |
---|
533 | |
---|
534 | (define_expand "umulsidi3" |
---|
535 | [(set (reg:DI 20) |
---|
536 | (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "")) |
---|
537 | (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))) |
---|
538 | (set (match_operand:DI 0 "arith_reg_operand" "") |
---|
539 | (reg:DI 20))] |
---|
540 | "TARGET_SH2" |
---|
541 | "") |
---|
542 | |
---|
543 | (define_insn "" |
---|
544 | [(set (reg:SI 20) |
---|
545 | (truncate:SI |
---|
546 | (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")) |
---|
547 | (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))) |
---|
548 | (const_int 32)))) |
---|
549 | (clobber (reg:SI 21))] |
---|
550 | "TARGET_SH2" |
---|
551 | "dmuls.l %2,%1" |
---|
552 | [(set_attr "type" "dmpy")]) |
---|
553 | |
---|
554 | (define_expand "smulsi3_highpart" |
---|
555 | [(parallel [(set (reg:SI 20) |
---|
556 | (truncate:SI |
---|
557 | (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "")) |
---|
558 | (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))) |
---|
559 | (const_int 32)))) |
---|
560 | (clobber (reg:SI 21))]) |
---|
561 | (set (match_operand:SI 0 "arith_reg_operand" "") |
---|
562 | (reg:SI 20))] |
---|
563 | "TARGET_SH2" |
---|
564 | "") |
---|
565 | |
---|
566 | (define_insn "" |
---|
567 | [(set (reg:SI 20) |
---|
568 | (truncate:SI |
---|
569 | (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")) |
---|
570 | (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))) |
---|
571 | (const_int 32)))) |
---|
572 | (clobber (reg:SI 21))] |
---|
573 | "TARGET_SH2" |
---|
574 | "dmulu.l %2,%1" |
---|
575 | [(set_attr "type" "dmpy")]) |
---|
576 | |
---|
577 | (define_expand "umulsi3_highpart" |
---|
578 | [(parallel [(set (reg:SI 20) |
---|
579 | (truncate:SI |
---|
580 | (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "")) |
---|
581 | (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))) |
---|
582 | (const_int 32)))) |
---|
583 | (clobber (reg:SI 21))]) |
---|
584 | (set (match_operand:SI 0 "arith_reg_operand" "") |
---|
585 | (reg:SI 20))] |
---|
586 | "TARGET_SH2" |
---|
587 | "") |
---|
588 | |
---|
589 | ;; ------------------------------------------------------------------------- |
---|
590 | ;; Logical operations |
---|
591 | ;; ------------------------------------------------------------------------- |
---|
592 | |
---|
593 | (define_insn "" |
---|
594 | [(set (match_operand:SI 0 "arith_reg_operand" "=r,z") |
---|
595 | (and:SI (match_operand:SI 1 "arith_reg_operand" "%0,0") |
---|
596 | (match_operand:SI 2 "logical_operand" "r,L")))] |
---|
597 | "" |
---|
598 | "and %2,%0" |
---|
599 | [(set_attr "type" "arith")]) |
---|
600 | |
---|
601 | ;; If the constant is 255, then emit a extu.b instruction instead of an |
---|
602 | ;; and, since that will give better code. |
---|
603 | |
---|
604 | (define_expand "andsi3" |
---|
605 | [(set (match_operand:SI 0 "arith_reg_operand" "") |
---|
606 | (and:SI (match_operand:SI 1 "arith_reg_operand" "") |
---|
607 | (match_operand:SI 2 "logical_operand" "")))] |
---|
608 | "" |
---|
609 | " |
---|
610 | { |
---|
611 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 255) |
---|
612 | { |
---|
613 | emit_insn (gen_zero_extendqisi2 (operands[0], |
---|
614 | gen_lowpart (QImode, operands[1]))); |
---|
615 | DONE; |
---|
616 | } |
---|
617 | }") |
---|
618 | |
---|
619 | (define_insn "iorsi3" |
---|
620 | [(set (match_operand:SI 0 "arith_reg_operand" "=r,z") |
---|
621 | (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0") |
---|
622 | (match_operand:SI 2 "logical_operand" "r,L")))] |
---|
623 | "" |
---|
624 | "or %2,%0") |
---|
625 | |
---|
626 | (define_insn "xorsi3" |
---|
627 | [(set (match_operand:SI 0 "arith_reg_operand" "=z,r") |
---|
628 | (xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0") |
---|
629 | (match_operand:SI 2 "logical_operand" "L,r")))] |
---|
630 | "" |
---|
631 | "xor %2,%0" |
---|
632 | [(set_attr "type" "arith")]) |
---|
633 | |
---|
634 | ;; ------------------------------------------------------------------------- |
---|
635 | ;; Shifts and rotates |
---|
636 | ;; ------------------------------------------------------------------------- |
---|
637 | |
---|
638 | (define_insn "rotlsi3_1" |
---|
639 | [(set (match_operand:SI 0 "arith_reg_operand" "=r") |
---|
640 | (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0") |
---|
641 | (const_int 1))) |
---|
642 | (set (reg:SI 18) |
---|
643 | (lshiftrt:SI (match_dup 1) (const_int 31)))] |
---|
644 | "" |
---|
645 | "rotl %0") |
---|
646 | |
---|
647 | (define_insn "rotlsi3_31" |
---|
648 | [(set (match_operand:SI 0 "arith_reg_operand" "=r") |
---|
649 | (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0") |
---|
650 | (const_int 31))) |
---|
651 | (clobber (reg:SI 18))] |
---|
652 | "" |
---|
653 | "rotr %0") |
---|
654 | |
---|
655 | (define_insn "" |
---|
656 | [(set (match_operand:SI 0 "arith_reg_operand" "=r") |
---|
657 | (rotate:SI (match_operand:SI 1 "arith_reg_operand" "r") |
---|
658 | (const_int 16)))] |
---|
659 | "" |
---|
660 | "swap.w %1,%0") |
---|
661 | |
---|
662 | (define_expand "rotlsi3" |
---|
663 | [(set (match_operand:SI 0 "arith_reg_operand" "") |
---|
664 | (rotate:SI (match_operand:SI 1 "arith_reg_operand" "") |
---|
665 | (match_operand:SI 2 "immediate_operand" "")))] |
---|
666 | "" |
---|
667 | " |
---|
668 | { |
---|
669 | if (GET_CODE (operands[2]) != CONST_INT) |
---|
670 | FAIL; |
---|
671 | |
---|
672 | if (INTVAL (operands[2]) == 1) |
---|
673 | { |
---|
674 | emit_insn (gen_rotlsi3_1 (operands[0], operands[1])); |
---|
675 | DONE; |
---|
676 | } |
---|
677 | else if (INTVAL (operands[2]) == 31) |
---|
678 | { |
---|
679 | emit_insn (gen_rotlsi3_31 (operands[0], operands[1])); |
---|
680 | DONE; |
---|
681 | } |
---|
682 | else if (INTVAL (operands[2]) != 16) |
---|
683 | FAIL; |
---|
684 | }") |
---|
685 | |
---|
686 | (define_insn "" |
---|
687 | [(set (match_operand:HI 0 "arith_reg_operand" "=r") |
---|
688 | (rotate:HI (match_operand:HI 1 "arith_reg_operand" "r") |
---|
689 | (const_int 8)))] |
---|
690 | "" |
---|
691 | "swap.b %1,%0") |
---|
692 | |
---|
693 | (define_expand "rotlhi3" |
---|
694 | [(set (match_operand:HI 0 "arith_reg_operand" "") |
---|
695 | (rotate:HI (match_operand:HI 1 "arith_reg_operand" "") |
---|
696 | (match_operand:HI 2 "immediate_operand" "")))] |
---|
697 | "" |
---|
698 | " |
---|
699 | { |
---|
700 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 8) |
---|
701 | FAIL; |
---|
702 | }") |
---|
703 | |
---|
704 | ;; |
---|
705 | ;; shift left |
---|
706 | |
---|
707 | (define_insn "ashlsi3_d" |
---|
708 | [(set (match_operand:SI 0 "arith_reg_operand" "=r") |
---|
709 | (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") |
---|
710 | (match_operand:SI 2 "arith_reg_operand" "r")))] |
---|
711 | "TARGET_SH3" |
---|
712 | "shld %2,%0") |
---|
713 | |
---|
714 | (define_insn "ashlsi3_k" |
---|
715 | [(set (match_operand:SI 0 "arith_reg_operand" "=r,r") |
---|
716 | (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0") |
---|
717 | (match_operand:SI 2 "const_int_operand" "M,K")))] |
---|
718 | "CONST_OK_FOR_K (INTVAL (operands[2]))" |
---|
719 | "@ |
---|
720 | add %0,%0 |
---|
721 | shll%O2 %0") |
---|
722 | |
---|
723 | (define_insn "ashlsi3_n" |
---|
724 | [(set (match_operand:SI 0 "arith_reg_operand" "=r") |
---|
725 | (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") |
---|
726 | (match_operand:SI 2 "const_int_operand" "n"))) |
---|
727 | (clobber (reg:SI 18))] |
---|
728 | "" |
---|
729 | "#" |
---|
730 | [(set (attr "length") |
---|
731 | (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1)) |
---|
732 | (const_string "2") |
---|
733 | (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2)) |
---|
734 | (const_string "4") |
---|
735 | (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3)) |
---|
736 | (const_string "6")] |
---|
737 | (const_string "8"))) |
---|
738 | (set_attr "type" "arith")]) |
---|
739 | |
---|
740 | (define_split |
---|
741 | [(set (match_operand:SI 0 "arith_reg_operand" "") |
---|
742 | (ashift:SI (match_operand:SI 1 "arith_reg_operand" "") |
---|
743 | (match_operand:SI 2 "const_int_operand" "n"))) |
---|
744 | (clobber (reg:SI 18))] |
---|
745 | "" |
---|
746 | [(use (reg:SI 0))] |
---|
747 | " |
---|
748 | { |
---|
749 | gen_shifty_op (ASHIFT, operands); |
---|
750 | DONE; |
---|
751 | }") |
---|
752 | |
---|
753 | (define_expand "ashlsi3" |
---|
754 | [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "") |
---|
755 | (ashift:SI (match_operand:SI 1 "arith_reg_operand" "") |
---|
756 | (match_operand:SI 2 "nonmemory_operand" ""))) |
---|
757 | (clobber (reg:SI 18))])] |
---|
758 | "" |
---|
759 | " |
---|
760 | { |
---|
761 | if (TARGET_SH3 && arith_reg_operand (operands[2], GET_MODE (operands[2]))) |
---|
762 | { |
---|
763 | emit_insn (gen_ashlsi3_d (operands[0], operands[1], operands[2])); |
---|
764 | DONE; |
---|
765 | } |
---|
766 | if (! immediate_operand (operands[2], GET_MODE (operands[2]))) |
---|
767 | FAIL; |
---|
768 | }") |
---|
769 | |
---|
770 | ; |
---|
771 | ; arithmetic shift right |
---|
772 | ; |
---|
773 | |
---|
774 | (define_insn "ashrsi3_k" |
---|
775 | [(set (match_operand:SI 0 "arith_reg_operand" "=r") |
---|
776 | (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0") |
---|
777 | (match_operand:SI 2 "const_int_operand" "M"))) |
---|
778 | (clobber (reg:SI 18))] |
---|
779 | "INTVAL (operands[2]) == 1" |
---|
780 | "shar %0" |
---|
781 | [(set_attr "type" "arith")]) |
---|
782 | |
---|
783 | ;; ??? This should be a define expand. |
---|
784 | |
---|
785 | (define_insn "ashrsi2_16" |
---|
786 | [(set (match_operand:SI 0 "arith_reg_operand" "=r") |
---|
787 | (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r") |
---|
788 | (const_int 16)))] |
---|
789 | "" |
---|
790 | "swap.w %1,%0\;exts.w %0,%0" |
---|
791 | [(set_attr "length" "4")]) |
---|
792 | |
---|
793 | ;; ??? This should be a define expand. |
---|
794 | |
---|
795 | (define_insn "ashrsi2_31" |
---|
796 | [(set (match_operand:SI 0 "arith_reg_operand" "=r") |
---|
797 | (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0") |
---|
798 | (const_int 31))) |
---|
799 | (clobber (reg:SI 18))] |
---|
800 | "" |
---|
801 | "@ |
---|
802 | shll %0\;subc %0,%0" |
---|
803 | [(set_attr "length" "4")]) |
---|
804 | |
---|
805 | (define_insn "ashrsi3_d" |
---|
806 | [(set (match_operand:SI 0 "arith_reg_operand" "=r") |
---|
807 | (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0") |
---|
808 | (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))] |
---|
809 | "TARGET_SH3" |
---|
810 | "shad %2,%1") |
---|
811 | |
---|
812 | (define_insn "ashrsi3_n" |
---|
813 | [(set (reg:SI 4) |
---|
814 | (ashiftrt:SI (reg:SI 4) |
---|
815 | (match_operand:SI 0 "const_int_operand" "i"))) |
---|
816 | (clobber (reg:SI 18)) |
---|
817 | (clobber (reg:SI 17)) |
---|
818 | (use (match_operand:SI 1 "arith_reg_operand" "r"))] |
---|
819 | "" |
---|
820 | "jsr @%1%#" |
---|
821 | [(set_attr "type" "sfunc") |
---|
822 | (set_attr "needs_delay_slot" "yes")]) |
---|
823 | |
---|
824 | (define_expand "ashrsi3" |
---|
825 | [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "") |
---|
826 | (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "") |
---|
827 | (match_operand:SI 2 "nonmemory_operand" ""))) |
---|
828 | (clobber (reg:SI 18))])] |
---|
829 | "" |
---|
830 | "if (expand_ashiftrt (operands)) DONE; else FAIL;") |
---|
831 | |
---|
832 | ;; logical shift right |
---|
833 | |
---|
834 | (define_insn "lshrsi3_d" |
---|
835 | [(set (match_operand:SI 0 "arith_reg_operand" "=r") |
---|
836 | (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0") |
---|
837 | (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))] |
---|
838 | "TARGET_SH3" |
---|
839 | "shld %2,%0") |
---|
840 | |
---|
841 | ;; Only the single bit shift clobbers the T bit. |
---|
842 | |
---|
843 | (define_insn "lshrsi3_m" |
---|
844 | [(set (match_operand:SI 0 "arith_reg_operand" "=r") |
---|
845 | (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0") |
---|
846 | (match_operand:SI 2 "const_int_operand" "M"))) |
---|
847 | (clobber (reg:SI 18))] |
---|
848 | "CONST_OK_FOR_M (INTVAL (operands[2]))" |
---|
849 | "shlr %0") |
---|
850 | |
---|
851 | (define_insn "lshrsi3_k" |
---|
852 | [(set (match_operand:SI 0 "arith_reg_operand" "=r") |
---|
853 | (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0") |
---|
854 | (match_operand:SI 2 "const_int_operand" "K")))] |
---|
855 | "CONST_OK_FOR_K (INTVAL (operands[2])) |
---|
856 | && ! CONST_OK_FOR_M (INTVAL (operands[2]))" |
---|
857 | "shlr%O2 %0") |
---|
858 | |
---|
859 | (define_insn "lshrsi3_n" |
---|
860 | [(set (match_operand:SI 0 "arith_reg_operand" "=r") |
---|
861 | (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0") |
---|
862 | (match_operand:SI 2 "const_int_operand" "n"))) |
---|
863 | (clobber (reg:SI 18))] |
---|
864 | "" |
---|
865 | "#" |
---|
866 | [(set (attr "length") |
---|
867 | (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1)) |
---|
868 | (const_string "2") |
---|
869 | (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2)) |
---|
870 | (const_string "4") |
---|
871 | (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3)) |
---|
872 | (const_string "6")] |
---|
873 | (const_string "8"))) |
---|
874 | (set_attr "type" "arith")]) |
---|
875 | |
---|
876 | (define_split |
---|
877 | [(set (match_operand:SI 0 "arith_reg_operand" "") |
---|
878 | (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "") |
---|
879 | (match_operand:SI 2 "const_int_operand" "n"))) |
---|
880 | (clobber (reg:SI 18))] |
---|
881 | "" |
---|
882 | [(use (reg:SI 0))] |
---|
883 | " |
---|
884 | { |
---|
885 | gen_shifty_op (LSHIFTRT, operands); |
---|
886 | DONE; |
---|
887 | }") |
---|
888 | |
---|
889 | (define_expand "lshrsi3" |
---|
890 | [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "") |
---|
891 | (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "") |
---|
892 | (match_operand:SI 2 "nonmemory_operand" ""))) |
---|
893 | (clobber (reg:SI 18))])] |
---|
894 | "" |
---|
895 | " |
---|
896 | { |
---|
897 | if (TARGET_SH3 && arith_reg_operand (operands[2], GET_MODE (operands[2]))) |
---|
898 | { |
---|
899 | rtx count = copy_to_mode_reg (SImode, operands[2]); |
---|
900 | emit_insn (gen_negsi2 (count, count)); |
---|
901 | emit_insn (gen_ashlsi3_d (operands[0], operands[1], count)); |
---|
902 | DONE; |
---|
903 | } |
---|
904 | if (! immediate_operand (operands[2], GET_MODE (operands[2]))) |
---|
905 | FAIL; |
---|
906 | }") |
---|
907 | |
---|
908 | ;; ??? This should be a define expand. |
---|
909 | |
---|
910 | (define_insn "ashldi3_k" |
---|
911 | [(set (match_operand:DI 0 "arith_reg_operand" "=r") |
---|
912 | (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0") |
---|
913 | (const_int 1))) |
---|
914 | (clobber (reg:SI 18))] |
---|
915 | "" |
---|
916 | "shll %R0\;rotcl %S0" |
---|
917 | [(set_attr "length" "4")]) |
---|
918 | |
---|
919 | (define_expand "ashldi3" |
---|
920 | [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "") |
---|
921 | (ashift:DI (match_operand:DI 1 "arith_reg_operand" "") |
---|
922 | (match_operand:DI 2 "immediate_operand" ""))) |
---|
923 | (clobber (reg:SI 18))])] |
---|
924 | "" |
---|
925 | "{ if (GET_CODE (operands[2]) != CONST_INT |
---|
926 | || INTVAL (operands[2]) != 1) FAIL;} ") |
---|
927 | |
---|
928 | ;; ??? This should be a define expand. |
---|
929 | |
---|
930 | (define_insn "lshrdi3_k" |
---|
931 | [(set (match_operand:DI 0 "arith_reg_operand" "=r") |
---|
932 | (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0") |
---|
933 | (const_int 1))) |
---|
934 | (clobber (reg:SI 18))] |
---|
935 | "" |
---|
936 | "shlr %S0\;rotcr %R0" |
---|
937 | [(set_attr "length" "4")]) |
---|
938 | |
---|
939 | (define_expand "lshrdi3" |
---|
940 | [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "") |
---|
941 | (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "") |
---|
942 | (match_operand:DI 2 "immediate_operand" ""))) |
---|
943 | (clobber (reg:SI 18))])] |
---|
944 | "" |
---|
945 | "{ if (GET_CODE (operands[2]) != CONST_INT |
---|
946 | || INTVAL (operands[2]) != 1) FAIL;} ") |
---|
947 | |
---|
948 | ;; ??? This should be a define expand. |
---|
949 | |
---|
950 | (define_insn "ashrdi3_k" |
---|
951 | [(set (match_operand:DI 0 "arith_reg_operand" "=r") |
---|
952 | (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0") |
---|
953 | (const_int 1))) |
---|
954 | (clobber (reg:SI 18))] |
---|
955 | "" |
---|
956 | "shar %S0\;rotcr %R0" |
---|
957 | [(set_attr "length" "4")]) |
---|
958 | |
---|
959 | (define_expand "ashrdi3" |
---|
960 | [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "") |
---|
961 | (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "") |
---|
962 | (match_operand:DI 2 "immediate_operand" ""))) |
---|
963 | (clobber (reg:SI 18))])] |
---|
964 | "" |
---|
965 | "{ if (GET_CODE (operands[2]) != CONST_INT |
---|
966 | || INTVAL (operands[2]) != 1) FAIL; } ") |
---|
967 | |
---|
968 | ;; ------------------------------------------------------------------------- |
---|
969 | ;; Unary arithmetic |
---|
970 | ;; ------------------------------------------------------------------------- |
---|
971 | |
---|
972 | (define_insn "negc" |
---|
973 | [(set (match_operand:SI 0 "arith_reg_operand" "=r") |
---|
974 | (neg:SI (plus:SI (reg:SI 18) |
---|
975 | (match_operand:SI 1 "arith_reg_operand" "r")))) |
---|
976 | (set (reg:SI 18) |
---|
977 | (ne:SI (ior:SI (reg:SI 18) (match_dup 1)) |
---|
978 | (const_int 0)))] |
---|
979 | "" |
---|
980 | "negc %1,%0" |
---|
981 | [(set_attr "type" "arith")]) |
---|
982 | |
---|
983 | (define_expand "negdi2" |
---|
984 | [(set (match_operand:DI 0 "arith_reg_operand" "") |
---|
985 | (neg:DI (match_operand:DI 1 "arith_reg_operand" ""))) |
---|
986 | (clobber (reg:SI 18))] |
---|
987 | "" |
---|
988 | " |
---|
989 | { |
---|
990 | int low_word = (TARGET_LITTLE_ENDIAN ? 0 : 1); |
---|
991 | int high_word = (TARGET_LITTLE_ENDIAN ? 1 : 0); |
---|
992 | |
---|
993 | rtx low_src = operand_subword (operands[1], low_word, 0, DImode); |
---|
994 | rtx high_src = operand_subword (operands[1], high_word, 0, DImode); |
---|
995 | |
---|
996 | rtx low_dst = operand_subword (operands[0], low_word, 1, DImode); |
---|
997 | rtx high_dst = operand_subword (operands[0], high_word, 1, DImode); |
---|
998 | |
---|
999 | emit_insn (gen_clrt ()); |
---|
1000 | emit_insn (gen_negc (low_dst, low_src)); |
---|
1001 | emit_insn (gen_negc (high_dst, high_src)); |
---|
1002 | DONE; |
---|
1003 | }") |
---|
1004 | |
---|
1005 | (define_insn "negsi2" |
---|
1006 | [(set (match_operand:SI 0 "arith_reg_operand" "=r") |
---|
1007 | (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))] |
---|
1008 | "" |
---|
1009 | "neg %1,%0" |
---|
1010 | [(set_attr "type" "arith")]) |
---|
1011 | |
---|
1012 | (define_insn "one_cmplsi2" |
---|
1013 | [(set (match_operand:SI 0 "arith_reg_operand" "=r") |
---|
1014 | (not:SI (match_operand:SI 1 "arith_reg_operand" "r")))] |
---|
1015 | "" |
---|
1016 | "not %1,%0" |
---|
1017 | [(set_attr "type" "arith")]) |
---|
1018 | |
---|
1019 | ;; ------------------------------------------------------------------------- |
---|
1020 | ;; Zero extension instructions |
---|
1021 | ;; ------------------------------------------------------------------------- |
---|
1022 | |
---|
1023 | (define_insn "zero_extendhisi2" |
---|
1024 | [(set (match_operand:SI 0 "arith_reg_operand" "=r") |
---|
1025 | (zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r")))] |
---|
1026 | "" |
---|
1027 | "extu.w %1,%0" |
---|
1028 | [(set_attr "type" "arith")]) |
---|
1029 | |
---|
1030 | (define_insn "zero_extendqisi2" |
---|
1031 | [(set (match_operand:SI 0 "arith_reg_operand" "=r") |
---|
1032 | (zero_extend:SI (match_operand:QI 1 "arith_reg_operand" "r")))] |
---|
1033 | "" |
---|
1034 | "extu.b %1,%0" |
---|
1035 | [(set_attr "type" "arith")]) |
---|
1036 | |
---|
1037 | (define_insn "zero_extendqihi2" |
---|
1038 | [(set (match_operand:HI 0 "arith_reg_operand" "=r") |
---|
1039 | (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))] |
---|
1040 | "" |
---|
1041 | "extu.b %1,%0" |
---|
1042 | [(set_attr "type" "arith")]) |
---|
1043 | |
---|
1044 | ;; ------------------------------------------------------------------------- |
---|
1045 | ;; Sign extension instructions |
---|
1046 | ;; ------------------------------------------------------------------------- |
---|
1047 | |
---|
1048 | ;; ??? This should be a define expand. |
---|
1049 | ;; ??? Or perhaps it should be dropped? |
---|
1050 | |
---|
1051 | (define_insn "extendsidi2" |
---|
1052 | [(set (match_operand:DI 0 "arith_reg_operand" "=r") |
---|
1053 | (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))) |
---|
1054 | (clobber (reg:SI 18))] |
---|
1055 | "" |
---|
1056 | "mov %1,%S0\;mov %1,%R0\;shll %S0\;subc %S0,%S0" |
---|
1057 | [(set_attr "length" "8")]) |
---|
1058 | |
---|
1059 | (define_insn "extendhisi2" |
---|
1060 | [(set (match_operand:SI 0 "arith_reg_operand" "=r,r") |
---|
1061 | (sign_extend:SI (match_operand:HI 1 "general_movsrc_operand" "r,m")))] |
---|
1062 | "" |
---|
1063 | "@ |
---|
1064 | exts.w %1,%0 |
---|
1065 | mov.w %1,%0" |
---|
1066 | [(set_attr "type" "arith,load")]) |
---|
1067 | |
---|
1068 | (define_insn "extendqisi2" |
---|
1069 | [(set (match_operand:SI 0 "arith_reg_operand" "=r,r") |
---|
1070 | (sign_extend:SI (match_operand:QI 1 "general_movsrc_operand" "r,m")))] |
---|
1071 | "" |
---|
1072 | "@ |
---|
1073 | exts.b %1,%0 |
---|
1074 | mov.b %1,%0" |
---|
1075 | [(set_attr "type" "arith,load")]) |
---|
1076 | |
---|
1077 | (define_insn "extendqihi2" |
---|
1078 | [(set (match_operand:HI 0 "arith_reg_operand" "=r,r") |
---|
1079 | (sign_extend:HI (match_operand:QI 1 "general_movsrc_operand" "r,m")))] |
---|
1080 | "" |
---|
1081 | "@ |
---|
1082 | exts.b %1,%0 |
---|
1083 | mov.b %1,%0" |
---|
1084 | [(set_attr "type" "arith,load")]) |
---|
1085 | |
---|
1086 | ;; ------------------------------------------------------------------------- |
---|
1087 | ;; Move instructions |
---|
1088 | ;; ------------------------------------------------------------------------- |
---|
1089 | |
---|
1090 | ;; define push and pop so it is easy for sh.c |
---|
1091 | |
---|
1092 | (define_insn "push" |
---|
1093 | [(set (mem:SI (pre_dec:SI (reg:SI 15))) |
---|
1094 | (match_operand:SI 0 "register_operand" "r,l,x"))] |
---|
1095 | "" |
---|
1096 | "@ |
---|
1097 | mov.l %0,@-r15 |
---|
1098 | sts.l %0,@-r15 |
---|
1099 | sts.l %0,@-r15" |
---|
1100 | [(set_attr "type" "store,pstore,store") |
---|
1101 | (set_attr "hit_stack" "yes")]) |
---|
1102 | |
---|
1103 | (define_insn "pop" |
---|
1104 | [(set (match_operand:SI 0 "register_operand" "=r,l,x") |
---|
1105 | (mem:SI (post_inc:SI (reg:SI 15))))] |
---|
1106 | "" |
---|
1107 | "@ |
---|
1108 | mov.l @r15+,%0 |
---|
1109 | lds.l @r15+,%0 |
---|
1110 | lds.l @r15+,%0" |
---|
1111 | [(set_attr "type" "load,pload,load") |
---|
1112 | (set_attr "hit_stack" "yes")]) |
---|
1113 | |
---|
1114 | ;; These two patterns can happen as the result of optimization, when |
---|
1115 | ;; comparisons get simplified to a move of zero or 1 into the T reg. |
---|
1116 | ;; They don't disappear completely, because the T reg is a fixed hard reg. |
---|
1117 | |
---|
1118 | (define_insn "clrt" |
---|
1119 | [(set (reg:SI 18) (const_int 0))] |
---|
1120 | "" |
---|
1121 | "clrt") |
---|
1122 | |
---|
1123 | (define_insn "sett" |
---|
1124 | [(set (reg:SI 18) (const_int 1))] |
---|
1125 | "" |
---|
1126 | "sett") |
---|
1127 | |
---|
1128 | ;; t/z is first, so that it will be preferred over r/r when reloading a move |
---|
1129 | ;; of a pseudo-reg into the T reg |
---|
1130 | (define_insn "movsi_i" |
---|
1131 | [(set (match_operand:SI 0 "general_movdst_operand" "=t,r,r,r,r,r,m,<,xl,xl,r") |
---|
1132 | (match_operand:SI 1 "general_movsrc_operand" "z,Q,rI,m,xl,t,r,xl,r,>,i"))] |
---|
1133 | "register_operand (operands[0], SImode) |
---|
1134 | || register_operand (operands[1], SImode)" |
---|
1135 | "@ |
---|
1136 | tst %1,%1\;rotcl %1\;xor #1,%1\;rotcr %1 |
---|
1137 | mov.l %1,%0 |
---|
1138 | mov %1,%0 |
---|
1139 | mov.l %1,%0 |
---|
1140 | sts %1,%0 |
---|
1141 | movt %0 |
---|
1142 | mov.l %1,%0 |
---|
1143 | sts.l %1,%0 |
---|
1144 | lds %1,%0 |
---|
1145 | lds.l %1,%0 |
---|
1146 | fake %1,%0" |
---|
1147 | [(set_attr "type" "move,pcload,move,load,move,store,store,move,load,move,move") |
---|
1148 | (set_attr "length" "8,*,*,*,*,*,*,*,*,*,*")]) |
---|
1149 | |
---|
1150 | (define_expand "movsi" |
---|
1151 | [(set (match_operand:SI 0 "general_movdst_operand" "") |
---|
1152 | (match_operand:SI 1 "general_movsrc_operand" ""))] |
---|
1153 | "" |
---|
1154 | "{ if (prepare_move_operands (operands, SImode)) DONE; }") |
---|
1155 | |
---|
1156 | (define_insn "movqi_i" |
---|
1157 | [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,m,r,r,l") |
---|
1158 | (match_operand:QI 1 "general_movsrc_operand" "ri,m,r,t,l,r"))] |
---|
1159 | "arith_reg_operand (operands[0], QImode) |
---|
1160 | || arith_reg_operand (operands[1], QImode)" |
---|
1161 | "@ |
---|
1162 | mov %1,%0 |
---|
1163 | mov.b %1,%0 |
---|
1164 | mov.b %1,%0 |
---|
1165 | movt %0 |
---|
1166 | sts %1,%0 |
---|
1167 | lds %1,%0" |
---|
1168 | [(set_attr "type" "move,load,store,move,move,move")]) |
---|
1169 | |
---|
1170 | (define_expand "movqi" |
---|
1171 | [(set (match_operand:QI 0 "general_operand" "") |
---|
1172 | (match_operand:QI 1 "general_operand" ""))] |
---|
1173 | "" |
---|
1174 | "{ if (prepare_move_operands (operands, QImode)) DONE; }") |
---|
1175 | |
---|
1176 | (define_insn "movhi_i" |
---|
1177 | [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m,r,l,r") |
---|
1178 | (match_operand:HI 1 "general_movsrc_operand" "Q,rI,m,t,r,l,r,i"))] |
---|
1179 | "arith_reg_operand (operands[0], HImode) |
---|
1180 | || arith_reg_operand (operands[1], HImode)" |
---|
1181 | "@ |
---|
1182 | mov.w %1,%0 |
---|
1183 | mov %1,%0 |
---|
1184 | mov.w %1,%0 |
---|
1185 | movt %0 |
---|
1186 | mov.w %1,%0 |
---|
1187 | sts %1,%0 |
---|
1188 | lds %1,%0 |
---|
1189 | fake %1,%0" |
---|
1190 | [(set_attr "type" "pcload,move,load,move,store,move,move,move")]) |
---|
1191 | |
---|
1192 | (define_expand "movhi" |
---|
1193 | [(set (match_operand:HI 0 "general_movdst_operand" "") |
---|
1194 | (match_operand:HI 1 "general_movsrc_operand" ""))] |
---|
1195 | "" |
---|
1196 | "{ if (prepare_move_operands (operands, HImode)) DONE; }") |
---|
1197 | |
---|
1198 | ;; ??? This should be a define expand. |
---|
1199 | |
---|
1200 | (define_insn "" |
---|
1201 | [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m,r,r") |
---|
1202 | (match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,i,x"))] |
---|
1203 | "arith_reg_operand (operands[0], DImode) |
---|
1204 | || arith_reg_operand (operands[1], DImode)" |
---|
1205 | "* return output_movedouble (insn, operands, DImode);" |
---|
1206 | [(set_attr "length" "4") |
---|
1207 | (set_attr "type" "pcload,move,load,store,move,move")]) |
---|
1208 | |
---|
1209 | ;; If the output is a register and the input is memory or a register, we have |
---|
1210 | ;; to be careful and see which word needs to be loaded first. |
---|
1211 | |
---|
1212 | (define_split |
---|
1213 | [(set (match_operand:DI 0 "general_movdst_operand" "") |
---|
1214 | (match_operand:DI 1 "general_movsrc_operand" ""))] |
---|
1215 | "reload_completed" |
---|
1216 | [(set (match_dup 2) (match_dup 3)) |
---|
1217 | (set (match_dup 4) (match_dup 5))] |
---|
1218 | " |
---|
1219 | { |
---|
1220 | int regno; |
---|
1221 | |
---|
1222 | if ((GET_CODE (operands[0]) == MEM |
---|
1223 | && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) |
---|
1224 | || (GET_CODE (operands[1]) == MEM |
---|
1225 | && GET_CODE (XEXP (operands[1], 0)) == POST_INC)) |
---|
1226 | FAIL; |
---|
1227 | |
---|
1228 | if (GET_CODE (operands[0]) == REG) |
---|
1229 | regno = REGNO (operands[0]); |
---|
1230 | else if (GET_CODE (operands[0]) == SUBREG) |
---|
1231 | regno = REGNO (SUBREG_REG (operands[0])) + SUBREG_WORD (operands[0]); |
---|
1232 | else if (GET_CODE (operands[0]) == MEM) |
---|
1233 | regno = -1; |
---|
1234 | |
---|
1235 | if (regno == -1 |
---|
1236 | || ! refers_to_regno_p (regno, regno + 1, operands[1], 0)) |
---|
1237 | { |
---|
1238 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
---|
1239 | operands[3] = operand_subword (operands[1], 0, 0, DImode); |
---|
1240 | operands[4] = operand_subword (operands[0], 1, 0, DImode); |
---|
1241 | operands[5] = operand_subword (operands[1], 1, 0, DImode); |
---|
1242 | } |
---|
1243 | else |
---|
1244 | { |
---|
1245 | operands[2] = operand_subword (operands[0], 1, 0, DImode); |
---|
1246 | operands[3] = operand_subword (operands[1], 1, 0, DImode); |
---|
1247 | operands[4] = operand_subword (operands[0], 0, 0, DImode); |
---|
1248 | operands[5] = operand_subword (operands[1], 0, 0, DImode); |
---|
1249 | } |
---|
1250 | |
---|
1251 | if (operands[2] == 0 || operands[3] == 0 |
---|
1252 | || operands[4] == 0 || operands[5] == 0) |
---|
1253 | FAIL; |
---|
1254 | }") |
---|
1255 | |
---|
1256 | (define_expand "movdi" |
---|
1257 | [(set (match_operand:DI 0 "general_movdst_operand" "") |
---|
1258 | (match_operand:DI 1 "general_movsrc_operand" ""))] |
---|
1259 | "" |
---|
1260 | "{ if ( prepare_move_operands (operands, DImode)) DONE; }") |
---|
1261 | |
---|
1262 | ;; ??? This should be a define expand. |
---|
1263 | |
---|
1264 | (define_insn "movdf_k" |
---|
1265 | [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,m") |
---|
1266 | (match_operand:DF 1 "general_movsrc_operand" "r,m,r"))] |
---|
1267 | "arith_reg_operand (operands[0], DFmode) |
---|
1268 | || arith_reg_operand (operands[1], DFmode)" |
---|
1269 | "* return output_movedouble (insn, operands, DFmode);" |
---|
1270 | [(set_attr "length" "4") |
---|
1271 | (set_attr "type" "move,load,store")]) |
---|
1272 | |
---|
1273 | ;; If the output is a register and the input is memory or a register, we have |
---|
1274 | ;; to be careful and see which word needs to be loaded first. |
---|
1275 | |
---|
1276 | (define_split |
---|
1277 | [(set (match_operand:DF 0 "general_movdst_operand" "") |
---|
1278 | (match_operand:DF 1 "general_movsrc_operand" ""))] |
---|
1279 | "reload_completed" |
---|
1280 | [(set (match_dup 2) (match_dup 3)) |
---|
1281 | (set (match_dup 4) (match_dup 5))] |
---|
1282 | " |
---|
1283 | { |
---|
1284 | int regno; |
---|
1285 | |
---|
1286 | if ((GET_CODE (operands[0]) == MEM |
---|
1287 | && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) |
---|
1288 | || (GET_CODE (operands[1]) == MEM |
---|
1289 | && GET_CODE (XEXP (operands[1], 0)) == POST_INC)) |
---|
1290 | FAIL; |
---|
1291 | |
---|
1292 | if (GET_CODE (operands[0]) == REG) |
---|
1293 | regno = REGNO (operands[0]); |
---|
1294 | else if (GET_CODE (operands[0]) == SUBREG) |
---|
1295 | regno = REGNO (SUBREG_REG (operands[0])) + SUBREG_WORD (operands[0]); |
---|
1296 | else if (GET_CODE (operands[0]) == MEM) |
---|
1297 | regno = -1; |
---|
1298 | |
---|
1299 | if (regno == -1 |
---|
1300 | || ! refers_to_regno_p (regno, regno + 1, operands[1], 0)) |
---|
1301 | { |
---|
1302 | operands[2] = operand_subword (operands[0], 0, 0, DFmode); |
---|
1303 | operands[3] = operand_subword (operands[1], 0, 0, DFmode); |
---|
1304 | operands[4] = operand_subword (operands[0], 1, 0, DFmode); |
---|
1305 | operands[5] = operand_subword (operands[1], 1, 0, DFmode); |
---|
1306 | } |
---|
1307 | else |
---|
1308 | { |
---|
1309 | operands[2] = operand_subword (operands[0], 1, 0, DFmode); |
---|
1310 | operands[3] = operand_subword (operands[1], 1, 0, DFmode); |
---|
1311 | operands[4] = operand_subword (operands[0], 0, 0, DFmode); |
---|
1312 | operands[5] = operand_subword (operands[1], 0, 0, DFmode); |
---|
1313 | } |
---|
1314 | |
---|
1315 | if (operands[2] == 0 || operands[3] == 0 |
---|
1316 | || operands[4] == 0 || operands[5] == 0) |
---|
1317 | FAIL; |
---|
1318 | }") |
---|
1319 | |
---|
1320 | (define_expand "movdf" |
---|
1321 | [(set (match_operand:DF 0 "general_movdst_operand" "") |
---|
1322 | (match_operand:DF 1 "general_movsrc_operand" ""))] |
---|
1323 | "" |
---|
1324 | "{ if (prepare_move_operands (operands, DFmode)) DONE; }") |
---|
1325 | |
---|
1326 | (define_insn "movsf_i" |
---|
1327 | [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,m,l,r") |
---|
1328 | (match_operand:SF 1 "general_movsrc_operand" "r,I,m,r,r,l"))] |
---|
1329 | "arith_reg_operand (operands[0], SFmode) |
---|
1330 | || arith_reg_operand (operands[1], SFmode)" |
---|
1331 | "@ |
---|
1332 | mov %1,%0 |
---|
1333 | mov %1,%0 |
---|
1334 | mov.l %1,%0 |
---|
1335 | mov.l %1,%0 |
---|
1336 | lds %1,%0 |
---|
1337 | sts %1,%0" |
---|
1338 | [(set_attr "type" "move,move,load,store,move,move")]) |
---|
1339 | |
---|
1340 | (define_expand "movsf" |
---|
1341 | [(set (match_operand:SF 0 "general_movdst_operand" "") |
---|
1342 | (match_operand:SF 1 "general_movsrc_operand" ""))] |
---|
1343 | "" |
---|
1344 | "{ if (prepare_move_operands (operands, SFmode)) DONE; }") |
---|
1345 | |
---|
1346 | ;; ------------------------------------------------------------------------ |
---|
1347 | ;; Define the real conditional branch instructions. |
---|
1348 | ;; ------------------------------------------------------------------------ |
---|
1349 | |
---|
1350 | (define_insn "branch_true" |
---|
1351 | [(set (pc) (if_then_else (eq (reg:SI 18) (const_int 1)) |
---|
1352 | (label_ref (match_operand 0 "" "")) |
---|
1353 | (pc)))] |
---|
1354 | "" |
---|
1355 | "* return output_branch (1, insn, operands);" |
---|
1356 | [(set_attr "type" "cbranch")]) |
---|
1357 | |
---|
1358 | (define_insn "branch_false" |
---|
1359 | [(set (pc) (if_then_else (ne (reg:SI 18) (const_int 1)) |
---|
1360 | (label_ref (match_operand 0 "" "")) |
---|
1361 | (pc)))] |
---|
1362 | "" |
---|
1363 | "* return output_branch (0, insn, operands);" |
---|
1364 | [(set_attr "type" "cbranch")]) |
---|
1365 | |
---|
1366 | (define_insn "inverse_branch_true" |
---|
1367 | [(set (pc) (if_then_else (eq (reg:SI 18) (const_int 1)) |
---|
1368 | (pc) |
---|
1369 | (label_ref (match_operand 0 "" ""))))] |
---|
1370 | "" |
---|
1371 | "* return output_branch (0, insn, operands);" |
---|
1372 | [(set_attr "type" "cbranch")]) |
---|
1373 | |
---|
1374 | (define_insn "inverse_branch_false" |
---|
1375 | [(set (pc) (if_then_else (ne (reg:SI 18) (const_int 1)) |
---|
1376 | (pc) |
---|
1377 | (label_ref (match_operand 0 "" ""))))] |
---|
1378 | "" |
---|
1379 | "* return output_branch (1, insn, operands);" |
---|
1380 | [(set_attr "type" "cbranch")]) |
---|
1381 | |
---|
1382 | ;; Conditional branch insns |
---|
1383 | |
---|
1384 | (define_expand "beq" |
---|
1385 | [(set (reg:SI 18) (eq:SI (match_dup 1) (match_dup 2))) |
---|
1386 | (set (pc) |
---|
1387 | (if_then_else (eq (reg:SI 18) (const_int 1)) |
---|
1388 | (label_ref (match_operand 0 "" "")) |
---|
1389 | (pc)))] |
---|
1390 | "" |
---|
1391 | "from_compare (operands, EQ);") |
---|
1392 | |
---|
1393 | ; There is no bne compare, so we reverse the branch arms. |
---|
1394 | |
---|
1395 | (define_expand "bne" |
---|
1396 | [(set (reg:SI 18) (eq:SI (match_dup 1) (match_dup 2))) |
---|
1397 | (set (pc) |
---|
1398 | (if_then_else (eq (reg:SI 18) (const_int 1)) |
---|
1399 | (pc) |
---|
1400 | (label_ref (match_operand 0 "" ""))))] |
---|
1401 | "" |
---|
1402 | "from_compare (operands, NE);") |
---|
1403 | |
---|
1404 | (define_expand "bgt" |
---|
1405 | [(set (reg:SI 18) (gt:SI (match_dup 1) (match_dup 2))) |
---|
1406 | (set (pc) |
---|
1407 | (if_then_else (eq (reg:SI 18) (const_int 1)) |
---|
1408 | (label_ref (match_operand 0 "" "")) |
---|
1409 | (pc)))] |
---|
1410 | "" |
---|
1411 | "from_compare (operands, GT);") |
---|
1412 | |
---|
1413 | (define_expand "blt" |
---|
1414 | [(set (reg:SI 18) (ge:SI (match_dup 1) (match_dup 2))) |
---|
1415 | (set (pc) |
---|
1416 | (if_then_else (eq (reg:SI 18) (const_int 1)) |
---|
1417 | (pc) |
---|
1418 | (label_ref (match_operand 0 "" ""))))] |
---|
1419 | "" |
---|
1420 | "from_compare (operands, LT);") |
---|
1421 | |
---|
1422 | (define_expand "ble" |
---|
1423 | [(set (reg:SI 18) (gt:SI (match_dup 1) (match_dup 2))) |
---|
1424 | (set (pc) |
---|
1425 | (if_then_else (eq (reg:SI 18) (const_int 1)) |
---|
1426 | (pc) |
---|
1427 | (label_ref (match_operand 0 "" ""))))] |
---|
1428 | "" |
---|
1429 | "from_compare (operands, LE);") |
---|
1430 | |
---|
1431 | (define_expand "bge" |
---|
1432 | [(set (reg:SI 18) (ge:SI (match_dup 1) (match_dup 2))) |
---|
1433 | (set (pc) |
---|
1434 | (if_then_else (eq (reg:SI 18) (const_int 1)) |
---|
1435 | (label_ref (match_operand 0 "" "")) |
---|
1436 | (pc)))] |
---|
1437 | "" |
---|
1438 | "from_compare (operands, GE);") |
---|
1439 | |
---|
1440 | (define_expand "bgtu" |
---|
1441 | [(set (reg:SI 18) (gtu:SI (match_dup 1) (match_dup 2))) |
---|
1442 | (set (pc) |
---|
1443 | (if_then_else (eq (reg:SI 18) (const_int 1)) |
---|
1444 | (label_ref (match_operand 0 "" "")) |
---|
1445 | (pc)))] |
---|
1446 | "" |
---|
1447 | "from_compare (operands, GTU); ") |
---|
1448 | |
---|
1449 | (define_expand "bltu" |
---|
1450 | [(set (reg:SI 18) (geu:SI (match_dup 1) (match_dup 2))) |
---|
1451 | (set (pc) |
---|
1452 | (if_then_else (eq (reg:SI 18) (const_int 1)) |
---|
1453 | (pc) |
---|
1454 | (label_ref (match_operand 0 "" ""))))] |
---|
1455 | "" |
---|
1456 | "from_compare (operands, LTU);") |
---|
1457 | |
---|
1458 | (define_expand "bgeu" |
---|
1459 | [(set (reg:SI 18) (geu:SI (match_dup 1) (match_dup 2))) |
---|
1460 | (set (pc) |
---|
1461 | (if_then_else (eq (reg:SI 18) (const_int 1)) |
---|
1462 | (label_ref (match_operand 0 "" "")) |
---|
1463 | (pc)))] |
---|
1464 | "" |
---|
1465 | "from_compare (operands, GEU);") |
---|
1466 | |
---|
1467 | (define_expand "bleu" |
---|
1468 | [(set (reg:SI 18) (gtu:SI (match_dup 1) (match_dup 2))) |
---|
1469 | (set (pc) |
---|
1470 | (if_then_else (eq (reg:SI 18) (const_int 1)) |
---|
1471 | (pc) |
---|
1472 | (label_ref (match_operand 0 "" ""))))] |
---|
1473 | "" |
---|
1474 | "from_compare (operands, LEU);") |
---|
1475 | |
---|
1476 | ;; ------------------------------------------------------------------------ |
---|
1477 | ;; Jump and linkage insns |
---|
1478 | ;; ------------------------------------------------------------------------ |
---|
1479 | |
---|
1480 | (define_insn "jump" |
---|
1481 | [(set (pc) |
---|
1482 | (label_ref (match_operand 0 "" "")))] |
---|
1483 | "" |
---|
1484 | "* |
---|
1485 | { |
---|
1486 | /* The length is 16 if the delay slot is unfilled. */ |
---|
1487 | if (get_attr_length(insn) >= 14) |
---|
1488 | return output_far_jump(insn, operands[0]); |
---|
1489 | else |
---|
1490 | return \"bra %l0%#\"; |
---|
1491 | }" |
---|
1492 | [(set_attr "type" "jump") |
---|
1493 | (set_attr "needs_delay_slot" "yes")]) |
---|
1494 | |
---|
1495 | (define_insn "calli" |
---|
1496 | [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r")) |
---|
1497 | (match_operand 1 "" "")) |
---|
1498 | (clobber (reg:SI 17))] |
---|
1499 | "" |
---|
1500 | "jsr @%0%#" |
---|
1501 | [(set_attr "type" "call") |
---|
1502 | (set_attr "needs_delay_slot" "yes")]) |
---|
1503 | |
---|
1504 | (define_insn "call_valuei" |
---|
1505 | [(set (match_operand 0 "" "=rf") |
---|
1506 | (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r")) |
---|
1507 | (match_operand 2 "" ""))) |
---|
1508 | (clobber (reg:SI 17))] |
---|
1509 | "" |
---|
1510 | "jsr @%1%#" |
---|
1511 | [(set_attr "type" "call") |
---|
1512 | (set_attr "needs_delay_slot" "yes")]) |
---|
1513 | |
---|
1514 | (define_expand "call" |
---|
1515 | [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" "")) |
---|
1516 | (match_operand 1 "" "")) |
---|
1517 | (clobber (reg:SI 17))])] |
---|
1518 | "" |
---|
1519 | "operands[0] = force_reg (SImode, XEXP (operands[0], 0));") |
---|
1520 | |
---|
1521 | (define_expand "call_value" |
---|
1522 | [(parallel [(set (match_operand 0 "arith_reg_operand" "") |
---|
1523 | (call (mem:SI (match_operand 1 "arith_reg_operand" "")) |
---|
1524 | (match_operand 2 "" ""))) |
---|
1525 | (clobber (reg:SI 17))])] |
---|
1526 | "" |
---|
1527 | "operands[1] = force_reg (SImode, XEXP (operands[1], 0));") |
---|
1528 | |
---|
1529 | (define_insn "indirect_jump" |
---|
1530 | [(set (pc) |
---|
1531 | (match_operand:SI 0 "arith_reg_operand" "r"))] |
---|
1532 | "" |
---|
1533 | "jmp @%0%#" |
---|
1534 | [(set_attr "needs_delay_slot" "yes")]) |
---|
1535 | |
---|
1536 | ;; ------------------------------------------------------------------------ |
---|
1537 | ;; Misc insns |
---|
1538 | ;; ------------------------------------------------------------------------ |
---|
1539 | |
---|
1540 | ;; ??? This combiner pattern does not work, because combine does not combine |
---|
1541 | ;; instructions that set a hard register when SMALL_REGISTER_CLASSES is |
---|
1542 | ;; defined. Perhaps use a pseudo-reg for the T bit? |
---|
1543 | |
---|
1544 | (define_insn "dect" |
---|
1545 | [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "=r") |
---|
1546 | (plus:SI (match_dup 0) |
---|
1547 | (const_int -1))) |
---|
1548 | (set (reg:SI 18) |
---|
1549 | (eq:SI (plus:SI (match_dup 0) (const_int -1)) |
---|
1550 | (const_int 0)))])] |
---|
1551 | "TARGET_SH2" |
---|
1552 | "dt %0") |
---|
1553 | |
---|
1554 | (define_insn "nop" |
---|
1555 | [(const_int 0)] |
---|
1556 | "" |
---|
1557 | "nop") |
---|
1558 | |
---|
1559 | ;; Load address of a label. This is only generated by the casesi expand. |
---|
1560 | ;; This must use unspec, because this only works immediately before a casesi. |
---|
1561 | |
---|
1562 | (define_insn "mova" |
---|
1563 | [(set (reg:SI 0) |
---|
1564 | (unspec [(label_ref (match_operand 0 "" ""))] 1))] |
---|
1565 | "" |
---|
1566 | "mova %O0,r0" |
---|
1567 | [(set_attr "in_delay_slot" "no")]) |
---|
1568 | |
---|
1569 | ;; case instruction for switch statements. |
---|
1570 | |
---|
1571 | ;; Operand 0 is index |
---|
1572 | ;; operand 1 is the minimum bound |
---|
1573 | ;; operand 2 is the maximum bound - minimum bound + 1 |
---|
1574 | ;; operand 3 is CODE_LABEL for the table; |
---|
1575 | ;; operand 4 is the CODE_LABEL to go to if index out of range. |
---|
1576 | |
---|
1577 | ;; ??? There should be a barrier after the jump at the end. |
---|
1578 | |
---|
1579 | (define_expand "casesi" |
---|
1580 | [(set (match_dup 5) (match_operand:SI 0 "arith_reg_operand" "")) |
---|
1581 | (set (match_dup 5) (minus:SI (match_dup 5) |
---|
1582 | (match_operand:SI 1 "arith_operand" ""))) |
---|
1583 | (set (reg:SI 18) |
---|
1584 | (gtu:SI (match_dup 5) |
---|
1585 | (match_operand:SI 2 "arith_reg_operand" ""))) |
---|
1586 | (set (pc) |
---|
1587 | (if_then_else (eq (reg:SI 18) |
---|
1588 | (const_int 1)) |
---|
1589 | (label_ref (match_operand 4 "" "")) |
---|
1590 | (pc))) |
---|
1591 | (set (match_dup 6) (match_dup 5)) |
---|
1592 | (set (match_dup 6) (ashift:SI (match_dup 6) (match_dup 7))) |
---|
1593 | (set (reg:SI 0) (unspec [(label_ref (match_operand 3 "" ""))] 1)) |
---|
1594 | (parallel [(set (reg:SI 0) (plus:SI (reg:SI 0) |
---|
1595 | (mem:HI (plus:SI (reg:SI 0) |
---|
1596 | (match_dup 6))))) |
---|
1597 | (set (match_dup 6) (mem:HI (plus:SI (reg:SI 0) (match_dup 6))))]) |
---|
1598 | (set (pc) (reg:SI 0))] |
---|
1599 | "" |
---|
1600 | " |
---|
1601 | { |
---|
1602 | operands[1] = copy_to_mode_reg (SImode, operands[1]); |
---|
1603 | operands[2] = copy_to_mode_reg (SImode, operands[2]); |
---|
1604 | operands[5] = gen_reg_rtx (SImode); |
---|
1605 | operands[6] = gen_reg_rtx (SImode); |
---|
1606 | operands[7] = GEN_INT (TARGET_BIGTABLE ? 2 : 1); |
---|
1607 | }") |
---|
1608 | |
---|
1609 | (define_insn "casesi_worker" |
---|
1610 | [(set (reg:SI 0) |
---|
1611 | (plus:SI (reg:SI 0) |
---|
1612 | (mem:HI (plus:SI (reg:SI 0) |
---|
1613 | (match_operand:SI 0 "arith_reg_operand" "+r"))))) |
---|
1614 | (set (match_dup 0) (mem:HI (plus:SI (reg:SI 0) |
---|
1615 | (match_dup 0))))] |
---|
1616 | "" |
---|
1617 | "* |
---|
1618 | { |
---|
1619 | if (TARGET_BIGTABLE) |
---|
1620 | return \"mov.l @(r0,%0),%0\;add %0,r0\"; |
---|
1621 | else |
---|
1622 | return \"mov.w @(r0,%0),%0\;add %0,r0\"; |
---|
1623 | }" |
---|
1624 | [(set_attr "length" "4")]) |
---|
1625 | |
---|
1626 | (define_insn "return" |
---|
1627 | [(return)] |
---|
1628 | "reload_completed" |
---|
1629 | "%@ %#" |
---|
1630 | [(set_attr "type" "return") |
---|
1631 | (set_attr "needs_delay_slot" "yes")]) |
---|
1632 | |
---|
1633 | (define_expand "prologue" |
---|
1634 | [(const_int 0)] |
---|
1635 | "" |
---|
1636 | "sh_expand_prologue (); DONE;") |
---|
1637 | |
---|
1638 | (define_expand "epilogue" |
---|
1639 | [(return)] |
---|
1640 | "" |
---|
1641 | "sh_expand_epilogue ();") |
---|
1642 | |
---|
1643 | (define_insn "blockage" |
---|
1644 | [(unspec_volatile [(const_int 0)] 0)] |
---|
1645 | "" |
---|
1646 | "" |
---|
1647 | [(set_attr "length" "0")]) |
---|
1648 | |
---|
1649 | ;; ------------------------------------------------------------------------ |
---|
1650 | ;; Scc instructions |
---|
1651 | ;; ------------------------------------------------------------------------ |
---|
1652 | |
---|
1653 | (define_insn "movt" |
---|
1654 | [(set (match_operand:SI 0 "arith_reg_operand" "=r") |
---|
1655 | (eq:SI (reg:SI 18) (const_int 1)))] |
---|
1656 | "" |
---|
1657 | "movt %0") |
---|
1658 | |
---|
1659 | (define_expand "seq" |
---|
1660 | [(set (match_operand:SI 0 "arith_reg_operand" "") |
---|
1661 | (match_dup 1))] |
---|
1662 | "" |
---|
1663 | "operands[1] = prepare_scc_operands (EQ);") |
---|
1664 | |
---|
1665 | (define_expand "slt" |
---|
1666 | [(set (match_operand:SI 0 "arith_reg_operand" "") |
---|
1667 | (match_dup 1))] |
---|
1668 | "" |
---|
1669 | "operands[1] = prepare_scc_operands (LT);") |
---|
1670 | |
---|
1671 | (define_expand "sle" |
---|
1672 | [(set (match_operand:SI 0 "arith_reg_operand" "") |
---|
1673 | (match_dup 1))] |
---|
1674 | "" |
---|
1675 | "operands[1] = prepare_scc_operands (LE);") |
---|
1676 | |
---|
1677 | (define_expand "sgt" |
---|
1678 | [(set (match_operand:SI 0 "arith_reg_operand" "") |
---|
1679 | (match_dup 1))] |
---|
1680 | "" |
---|
1681 | "operands[1] = prepare_scc_operands (GT);") |
---|
1682 | |
---|
1683 | (define_expand "sge" |
---|
1684 | [(set (match_operand:SI 0 "arith_reg_operand" "") |
---|
1685 | (match_dup 1))] |
---|
1686 | "" |
---|
1687 | "operands[1] = prepare_scc_operands (GE);") |
---|
1688 | |
---|
1689 | (define_expand "sgtu" |
---|
1690 | [(set (match_operand:SI 0 "arith_reg_operand" "") |
---|
1691 | (match_dup 1))] |
---|
1692 | "" |
---|
1693 | "operands[1] = prepare_scc_operands (GTU);") |
---|
1694 | |
---|
1695 | (define_expand "sltu" |
---|
1696 | [(set (match_operand:SI 0 "arith_reg_operand" "") |
---|
1697 | (match_dup 1))] |
---|
1698 | "" |
---|
1699 | "operands[1] = prepare_scc_operands (LTU);") |
---|
1700 | |
---|
1701 | (define_expand "sleu" |
---|
1702 | [(set (match_operand:SI 0 "arith_reg_operand" "") |
---|
1703 | (match_dup 1))] |
---|
1704 | "" |
---|
1705 | "operands[1] = prepare_scc_operands (LEU);") |
---|
1706 | |
---|
1707 | (define_expand "sgeu" |
---|
1708 | [(set (match_operand:SI 0 "arith_reg_operand" "") |
---|
1709 | (match_dup 1))] |
---|
1710 | "" |
---|
1711 | "operands[1] = prepare_scc_operands (GEU);") |
---|
1712 | |
---|
1713 | (define_expand "sne" |
---|
1714 | [(set (match_operand:SI 0 "arith_reg_operand" "") |
---|
1715 | (match_dup 1)) |
---|
1716 | (set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))] |
---|
1717 | "" |
---|
1718 | "operands[1] = prepare_scc_operands (EQ);") |
---|
1719 | |
---|
1720 | ;; ------------------------------------------------------------------------- |
---|
1721 | ;; Instructions to cope with inline literal tables |
---|
1722 | ;; ------------------------------------------------------------------------- |
---|
1723 | |
---|
1724 | ; 2 byte integer in line |
---|
1725 | |
---|
1726 | (define_insn "consttable_2" |
---|
1727 | [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")] 2)] |
---|
1728 | "" |
---|
1729 | "* |
---|
1730 | { |
---|
1731 | assemble_integer (operands[0], 2, 1); |
---|
1732 | return \"\"; |
---|
1733 | }" |
---|
1734 | [(set_attr "length" "2") |
---|
1735 | (set_attr "in_delay_slot" "no")]) |
---|
1736 | |
---|
1737 | ; 4 byte integer in line |
---|
1738 | |
---|
1739 | (define_insn "consttable_4" |
---|
1740 | [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")] 4)] |
---|
1741 | "" |
---|
1742 | "* |
---|
1743 | { |
---|
1744 | assemble_integer (operands[0], 4, 1); |
---|
1745 | return \"\"; |
---|
1746 | }" |
---|
1747 | [(set_attr "length" "4") |
---|
1748 | (set_attr "in_delay_slot" "no")]) |
---|
1749 | |
---|
1750 | ; 8 byte integer in line |
---|
1751 | |
---|
1752 | (define_insn "consttable_8" |
---|
1753 | [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")] 6)] |
---|
1754 | "" |
---|
1755 | "* |
---|
1756 | { |
---|
1757 | assemble_integer (operands[0], 8, 1); |
---|
1758 | return \"\"; |
---|
1759 | }" |
---|
1760 | [(set_attr "length" "8") |
---|
1761 | (set_attr "in_delay_slot" "no")]) |
---|
1762 | |
---|
1763 | ; align to a two byte boundary |
---|
1764 | |
---|
1765 | (define_insn "align_2" |
---|
1766 | [(unspec_volatile [(const_int 0)] 10)] |
---|
1767 | "" |
---|
1768 | ".align 1" |
---|
1769 | [(set_attr "length" "0") |
---|
1770 | (set_attr "in_delay_slot" "no")]) |
---|
1771 | |
---|
1772 | ; align to a four byte boundary |
---|
1773 | |
---|
1774 | (define_insn "align_4" |
---|
1775 | [(unspec_volatile [(const_int 0)] 5)] |
---|
1776 | "" |
---|
1777 | ".align 2" |
---|
1778 | [(set_attr "in_delay_slot" "no")]) |
---|
1779 | |
---|
1780 | ; emitted at the end of the literal table, used to emit the |
---|
1781 | ; 32bit branch labels if needed. |
---|
1782 | |
---|
1783 | (define_insn "consttable_end" |
---|
1784 | [(unspec_volatile [(const_int 0)] 11)] |
---|
1785 | "" |
---|
1786 | "* return output_jump_label_table ();" |
---|
1787 | [(set_attr "in_delay_slot" "no")]) |
---|
1788 | |
---|
1789 | ;; ------------------------------------------------------------------------- |
---|
1790 | ;; Misc |
---|
1791 | ;; ------------------------------------------------------------------------- |
---|
1792 | |
---|
1793 | ;; String/block move insn. |
---|
1794 | |
---|
1795 | (define_expand "movstrsi" |
---|
1796 | [(parallel [(set (mem:BLK (match_operand:BLK 0 "" "")) |
---|
1797 | (mem:BLK (match_operand:BLK 1 "" ""))) |
---|
1798 | (use (match_operand:SI 2 "nonmemory_operand" "")) |
---|
1799 | (use (match_operand:SI 3 "immediate_operand" "")) |
---|
1800 | (clobber (reg:SI 17)) |
---|
1801 | (clobber (reg:SI 4)) |
---|
1802 | (clobber (reg:SI 5)) |
---|
1803 | (clobber (reg:SI 0))])] |
---|
1804 | "" |
---|
1805 | " |
---|
1806 | { |
---|
1807 | if(expand_block_move (operands)) |
---|
1808 | DONE; |
---|
1809 | else FAIL; |
---|
1810 | }") |
---|
1811 | |
---|
1812 | (define_insn "block_move_real" |
---|
1813 | [(parallel [(set (mem:BLK (reg:SI 4)) |
---|
1814 | (mem:BLK (reg:SI 5))) |
---|
1815 | (use (match_operand:SI 0 "arith_reg_operand" "r")) |
---|
1816 | (clobber (reg:SI 17)) |
---|
1817 | (clobber (reg:SI 0))])] |
---|
1818 | "" |
---|
1819 | "jsr @%0%#" |
---|
1820 | [(set_attr "type" "sfunc") |
---|
1821 | (set_attr "needs_delay_slot" "yes")]) |
---|
1822 | |
---|
1823 | (define_insn "block_lump_real" |
---|
1824 | [(parallel [(set (mem:BLK (reg:SI 4)) |
---|
1825 | (mem:BLK (reg:SI 5))) |
---|
1826 | (use (match_operand:SI 0 "arith_reg_operand" "r")) |
---|
1827 | (use (reg:SI 6)) |
---|
1828 | (clobber (reg:SI 17)) |
---|
1829 | (clobber (reg:SI 4)) |
---|
1830 | (clobber (reg:SI 5)) |
---|
1831 | (clobber (reg:SI 6)) |
---|
1832 | (clobber (reg:SI 0))])] |
---|
1833 | "" |
---|
1834 | "jsr @%0%#" |
---|
1835 | [(set_attr "type" "sfunc") |
---|
1836 | (set_attr "needs_delay_slot" "yes")]) |
---|
1837 | |
---|
1838 | ;; ------------------------------------------------------------------------- |
---|
1839 | ;; Peepholes |
---|
1840 | ;; ------------------------------------------------------------------------- |
---|
1841 | |
---|
1842 | ;; This matches cases where a stack pointer increment at the start of the |
---|
1843 | ;; epilogue combines with a stack slot read loading the return value. |
---|
1844 | |
---|
1845 | (define_peephole |
---|
1846 | [(set (match_operand:SI 0 "arith_reg_operand" "") |
---|
1847 | (mem:SI (match_operand:SI 1 "arith_reg_operand" ""))) |
---|
1848 | (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))] |
---|
1849 | "REGNO (operands[1]) != REGNO (operands[0])" |
---|
1850 | "mov.l @%1+,%0") |
---|
1851 | |
---|
1852 | ;; See the comment on the dt combiner pattern above. |
---|
1853 | |
---|
1854 | (define_peephole |
---|
1855 | [(set (match_operand:SI 0 "arith_reg_operand" "=r") |
---|
1856 | (plus:SI (match_dup 0) |
---|
1857 | (const_int -1))) |
---|
1858 | (set (reg:SI 18) |
---|
1859 | (eq:SI (match_dup 0) |
---|
1860 | (const_int 0)))] |
---|
1861 | "TARGET_SH2" |
---|
1862 | "dt %0") |
---|
1863 | |
---|
1864 | ;; These convert sequences such as `mov #k,r0; add r15,r0; mov.l @r0,rn' |
---|
1865 | ;; to `mov #k,r0; mov.l @(r0,r15),rn'. These sequences are generated by |
---|
1866 | ;; reload when the constant is too large for a reg+offset address. |
---|
1867 | |
---|
1868 | ;; ??? We would get much better code if this was done in reload. This would |
---|
1869 | ;; require modifying find_reloads_address to recognize that if the constant |
---|
1870 | ;; is out-of-range for an immediate add, then we get better code by reloading |
---|
1871 | ;; the constant into a register than by reloading the sum into a register, |
---|
1872 | ;; since the former is one instruction shorter if the address does not need |
---|
1873 | ;; to be offsettable. Unfortunately this does not work, because there is |
---|
1874 | ;; only one register, r0, that can be used as an index register. This register |
---|
1875 | ;; is also the function return value register. So, if we try to force reload |
---|
1876 | ;; to use double-reg addresses, then we end up with some instructions that |
---|
1877 | ;; need to use r0 twice. The only way to fix this is to change the calling |
---|
1878 | ;; convention so that r0 is not used to return values. |
---|
1879 | |
---|
1880 | (define_peephole |
---|
1881 | [(set (match_operand:SI 0 "register_operand" "=r") |
---|
1882 | (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r"))) |
---|
1883 | (set (mem:SI (match_dup 0)) |
---|
1884 | (match_operand:SI 2 "general_movsrc_operand" ""))] |
---|
1885 | "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)" |
---|
1886 | "mov.l %2,@(%0,%1)") |
---|
1887 | |
---|
1888 | (define_peephole |
---|
1889 | [(set (match_operand:SI 0 "register_operand" "=r") |
---|
1890 | (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r"))) |
---|
1891 | (set (match_operand:SI 2 "general_movdst_operand" "") |
---|
1892 | (mem:SI (match_dup 0)))] |
---|
1893 | "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)" |
---|
1894 | "mov.l @(%0,%1),%2") |
---|
1895 | |
---|
1896 | (define_peephole |
---|
1897 | [(set (match_operand:SI 0 "register_operand" "=r") |
---|
1898 | (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r"))) |
---|
1899 | (set (mem:HI (match_dup 0)) |
---|
1900 | (match_operand:HI 2 "general_movsrc_operand" ""))] |
---|
1901 | "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)" |
---|
1902 | "mov.w %2,@(%0,%1)") |
---|
1903 | |
---|
1904 | (define_peephole |
---|
1905 | [(set (match_operand:SI 0 "register_operand" "=r") |
---|
1906 | (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r"))) |
---|
1907 | (set (match_operand:HI 2 "general_movdst_operand" "") |
---|
1908 | (mem:HI (match_dup 0)))] |
---|
1909 | "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)" |
---|
1910 | "mov.w @(%0,%1),%2") |
---|
1911 | |
---|
1912 | (define_peephole |
---|
1913 | [(set (match_operand:SI 0 "register_operand" "=r") |
---|
1914 | (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r"))) |
---|
1915 | (set (mem:QI (match_dup 0)) |
---|
1916 | (match_operand:QI 2 "general_movsrc_operand" ""))] |
---|
1917 | "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)" |
---|
1918 | "mov.b %2,@(%0,%1)") |
---|
1919 | |
---|
1920 | (define_peephole |
---|
1921 | [(set (match_operand:SI 0 "register_operand" "=r") |
---|
1922 | (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r"))) |
---|
1923 | (set (match_operand:QI 2 "general_movdst_operand" "") |
---|
1924 | (mem:QI (match_dup 0)))] |
---|
1925 | "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)" |
---|
1926 | "mov.b @(%0,%1),%2") |
---|
1927 | |
---|
1928 | (define_peephole |
---|
1929 | [(set (match_operand:SI 0 "register_operand" "=r") |
---|
1930 | (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r"))) |
---|
1931 | (set (mem:SF (match_dup 0)) |
---|
1932 | (match_operand:SF 2 "general_movsrc_operand" ""))] |
---|
1933 | "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)" |
---|
1934 | "mov.l %2,@(%0,%1)") |
---|
1935 | |
---|
1936 | (define_peephole |
---|
1937 | [(set (match_operand:SI 0 "register_operand" "=r") |
---|
1938 | (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r"))) |
---|
1939 | (set (match_operand:SF 2 "general_movdst_operand" "") |
---|
1940 | |
---|
1941 | (mem:SF (match_dup 0)))] |
---|
1942 | "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)" |
---|
1943 | "mov.l @(%0,%1),%2") |
---|