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Revision 8834, 34.5 KB checked in by ghudson, 28 years ago (diff)
This commit was generated by cvs2svn to compensate for changes in r8833, which included commits to RCS files with non-trunk default branches.

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1	;; Machine description for GNU compiler, AT&T we32000 Version
2	;; Copyright (C) 1991, 1992, 1994 Free Software Foundation, Inc.
3	;; Contributed by John Wehle (john@feith1.uucp)
4
5	;; This file is part of GNU CC.
6
7	;; GNU CC is free software; you can redistribute it and/or modify
8	;; it under the terms of the GNU General Public License as published by
9	;; the Free Software Foundation; either version 1, or (at your option)
10	;; any later version.
11
12	;; GNU CC is distributed in the hope that it will be useful,
13	;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14	;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15	;; GNU General Public License for more details.
16
17	;; You should have received a copy of the GNU General Public License
18	;; along with GNU CC; see the file COPYING. If not, write to
19	;; the Free Software Foundation, 59 Temple Place - Suite 330,
20	;; Boston, MA 02111-1307, USA.
21
22
23	;;- instruction definitions
24
25	;;- @@The original PO technology requires these to be ordered by speed,
26	;;- @@ so that assigner will pick the fastest.
27
28	;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29
30	;;- When naming insn's (operand 0 of define_insn) be careful about using
31	;;- names from other targets machine descriptions.
32
33	;; move instructions
34
35	(define_insn ""
36	[(set (match_operand:DF 0 "push_operand" "=m")
37	(match_operand:DF 1 "general_operand" "mrF"))]
38	""
39	"*
40	{
41	output_push_double(&operands[1]);
42
43	return \"\";
44	}")
45
46	(define_insn "movdf"
47	[(set (match_operand:DF 0 "nonimmediate_operand" "=mr")
48	(match_operand:DF 1 "general_operand" "mrF"))]
49	""
50	"*
51	{
52	output_move_double(operands);
53
54	return \"\";
55	}")
56
57	(define_insn ""
58	[(set (match_operand:SF 0 "push_operand" "=m")
59	(match_operand:SF 1 "general_operand" "mrF"))]
60	""
61	"pushw %1")
62
63	(define_insn "movsf"
64	[(set (match_operand:SF 0 "nonimmediate_operand" "=mr")
65	(match_operand:SF 1 "general_operand" "mrF"))]
66	""
67	"movw %1, %0")
68
69	(define_insn ""
70	[(set (match_operand:DI 0 "push_operand" "=m")
71	(match_operand:DI 1 "general_operand" "mriF"))]
72	""
73	"*
74	{
75	output_push_double(&operands[1]);
76
77	return \"\";
78	}")
79
80	(define_insn "movdi"
81	[(set (match_operand:DI 0 "nonimmediate_operand" "=mr")
82	(match_operand:DI 1 "general_operand" "mriF"))]
83	""
84	"*
85	{
86	output_move_double(operands);
87
88	return \"\";
89	}")
90
91	(define_insn ""
92	[(set (match_operand:SI 0 "push_operand" "=m")
93	(match_operand:SI 1 "general_operand" "mri"))]
94	""
95	"pushw %1")
96
97	(define_insn "movsi"
98	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
99	(match_operand:SI 1 "general_operand" "mri"))]
100	""
101	"movw %1, %0")
102
103	(define_insn "movhi"
104	[(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
105	(match_operand:HI 1 "general_operand" "mri"))]
106	""
107	"movh %1, %0")
108
109	(define_insn "movqi"
110	[(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
111	(match_operand:QI 1 "general_operand" "mri"))]
112	""
113	"movb %1, %0")
114
115	;; add instructions
116
117	(define_insn ""
118	[(set (match_operand:DI 0 "nonimmediate_operand" "=&or")
119	(plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
120	(match_operand:DI 2 "general_operand" "oriF")))]
121	""
122	"*
123	{
124	rtx label[1];
125	rtx lsw_operands[3];
126
127	if (GET_CODE (operands[0]) == REG)
128	lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1);
129	else
130	if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
131	lsw_operands[0] = adj_offsettable_operand(operands[0], 4);
132	else
133	abort();
134
135	if (GET_CODE (operands[2]) == REG)
136	lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1);
137	else
138	if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
139	lsw_operands[2] = adj_offsettable_operand(operands[2], 4);
140	else
141	if (GET_CODE (operands[2]) == CONST_DOUBLE)
142	{
143	lsw_operands[2] = gen_rtx(CONST_INT, SImode,
144	CONST_DOUBLE_HIGH(operands[2]));
145	operands[2] = gen_rtx(CONST_INT, SImode,
146	CONST_DOUBLE_LOW(operands[2]));
147	}
148	else
149	if (GET_CODE (operands[2]) == CONST_INT)
150	{
151	lsw_operands[2] = operands[2];
152	operands[2] = const0_rtx;
153	}
154	else
155	abort();
156
157	label[0] = gen_label_rtx();
158	LABEL_NUSES(label[0]) = 1;
159
160	output_asm_insn(\"addw2 %2, %0\", operands);
161	output_asm_insn(\"addw2 %2, %0\", lsw_operands);
162	output_asm_insn(\"BCCB %l0\", label);
163	output_asm_insn(\"INCW %0\", operands);
164	output_asm_insn(\"%l0:\", label);
165
166	return \"\";
167	}")
168
169	(define_insn "adddi3"
170	[(set (match_operand:DI 0 "nonimmediate_operand" "=&or")
171	(plus:DI (match_operand:DI 1 "general_operand" "oriF")
172	(match_operand:DI 2 "general_operand" "oriF")))]
173	""
174	"*
175	{
176	rtx label[1];
177	rtx lsw_operands[3];
178
179	if (GET_CODE (operands[0]) == REG)
180	lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1);
181	else
182	if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
183	lsw_operands[0] = adj_offsettable_operand(operands[0], 4);
184	else
185	abort();
186
187	if (GET_CODE (operands[1]) == REG)
188	lsw_operands[1] = gen_rtx(REG, SImode, REGNO (operands[1]) + 1);
189	else
190	if (GET_CODE (operands[1]) == MEM && offsettable_memref_p (operands[1]))
191	lsw_operands[1] = adj_offsettable_operand(operands[1], 4);
192	else
193	if (GET_CODE (operands[1]) == CONST_DOUBLE)
194	{
195	lsw_operands[1] = gen_rtx(CONST_INT, SImode,
196	CONST_DOUBLE_HIGH(operands[1]));
197	operands[1] = gen_rtx(CONST_INT, SImode,
198	CONST_DOUBLE_LOW(operands[1]));
199	}
200	else
201	if (GET_CODE (operands[1]) == CONST_INT)
202	{
203	lsw_operands[1] = operands[1];
204	operands[1] = const0_rtx;
205	}
206	else
207	abort();
208
209	if (GET_CODE (operands[2]) == REG)
210	lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1);
211	else
212	if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
213	lsw_operands[2] = adj_offsettable_operand(operands[2], 4);
214	else
215	if (GET_CODE (operands[2]) == CONST_DOUBLE)
216	{
217	lsw_operands[2] = gen_rtx(CONST_INT, SImode,
218	CONST_DOUBLE_HIGH(operands[2]));
219	operands[2] = gen_rtx(CONST_INT, SImode,
220	CONST_DOUBLE_LOW(operands[2]));
221	}
222	else
223	if (GET_CODE (operands[2]) == CONST_INT)
224	{
225	lsw_operands[2] = operands[2];
226	operands[2] = const0_rtx;
227	}
228	else
229	abort();
230
231	label[0] = gen_label_rtx();
232	LABEL_NUSES(label[0]) = 1;
233
234	output_asm_insn(\"addw3 %2, %1, %0\", operands);
235	output_asm_insn(\"addw3 %2, %1, %0\", lsw_operands);
236	output_asm_insn(\"BCCB %l0\", label);
237	output_asm_insn(\"INCW %0\", operands);
238	output_asm_insn(\"%l0:\", label);
239
240	return \"\";
241	}")
242
243	(define_insn ""
244	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
245	(plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
246	(match_operand:SI 2 "general_operand" "mri")))]
247	""
248	"addw2 %2, %0")
249
250	(define_insn "addsi3"
251	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
252	(plus:SI (match_operand:SI 1 "general_operand" "mri")
253	(match_operand:SI 2 "general_operand" "mri")))]
254	""
255	"addw3 %2, %1, %0")
256
257	(define_insn ""
258	[(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
259	(plus:HI (match_operand:HI 1 "nonimmediate_operand" "0")
260	(match_operand:HI 2 "general_operand" "mri")))]
261	""
262	"addh2 %2, %0")
263
264	(define_insn "addhi3"
265	[(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
266	(plus:HI (match_operand:HI 1 "general_operand" "mri")
267	(match_operand:HI 2 "general_operand" "mri")))]
268	""
269	"addh3 %2, %1, %0")
270
271	(define_insn ""
272	[(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
273	(plus:QI (match_operand:QI 1 "nonimmediate_operand" "0")
274	(match_operand:QI 2 "general_operand" "mri")))]
275	""
276	"addb2 %2, %0")
277
278	(define_insn "addqi3"
279	[(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
280	(plus:QI (match_operand:QI 1 "general_operand" "mri")
281	(match_operand:QI 2 "general_operand" "mri")))]
282	""
283	"addb3 %2, %1, %0")
284
285	;; subtract instructions
286
287	(define_insn ""
288	[(set (match_operand:DI 0 "nonimmediate_operand" "=&or")
289	(minus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
290	(match_operand:DI 2 "general_operand" "oriF")))]
291	""
292	"*
293	{
294	rtx label[1];
295	rtx lsw_operands[3];
296
297	if (GET_CODE (operands[0]) == REG)
298	lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1);
299	else
300	if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
301	lsw_operands[0] = adj_offsettable_operand(operands[0], 4);
302	else
303	abort();
304
305	if (GET_CODE (operands[2]) == REG)
306	lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1);
307	else
308	if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
309	lsw_operands[2] = adj_offsettable_operand(operands[2], 4);
310	else
311	if (GET_CODE (operands[2]) == CONST_DOUBLE)
312	{
313	lsw_operands[2] = gen_rtx(CONST_INT, SImode,
314	CONST_DOUBLE_HIGH(operands[2]));
315	operands[2] = gen_rtx(CONST_INT, SImode,
316	CONST_DOUBLE_LOW(operands[2]));
317	}
318	else
319	if (GET_CODE (operands[2]) == CONST_INT)
320	{
321	lsw_operands[2] = operands[2];
322	operands[2] = const0_rtx;
323	}
324	else
325	abort();
326
327	label[0] = gen_label_rtx();
328	LABEL_NUSES(label[0]) = 1;
329
330	output_asm_insn(\"subw2 %2, %0\", operands);
331	output_asm_insn(\"subw2 %2, %0\", lsw_operands);
332	output_asm_insn(\"BCCB %l0\", label);
333	output_asm_insn(\"DECW %0\", operands);
334	output_asm_insn(\"%l0:\", label);
335
336	return \"\";
337	}")
338
339	(define_insn "subdi3"
340	[(set (match_operand:DI 0 "nonimmediate_operand" "=&or")
341	(minus:DI (match_operand:DI 1 "general_operand" "oriF")
342	(match_operand:DI 2 "general_operand" "oriF")))]
343	""
344	"*
345	{
346	rtx label[1];
347	rtx lsw_operands[3];
348
349	if (GET_CODE (operands[0]) == REG)
350	lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1);
351	else
352	if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
353	lsw_operands[0] = adj_offsettable_operand(operands[0], 4);
354	else
355	abort();
356
357	if (GET_CODE (operands[1]) == REG)
358	lsw_operands[1] = gen_rtx(REG, SImode, REGNO (operands[1]) + 1);
359	else
360	if (GET_CODE (operands[1]) == MEM && offsettable_memref_p (operands[1]))
361	lsw_operands[1] = adj_offsettable_operand(operands[1], 4);
362	else
363	if (GET_CODE (operands[1]) == CONST_DOUBLE)
364	{
365	lsw_operands[1] = gen_rtx(CONST_INT, SImode,
366	CONST_DOUBLE_HIGH(operands[1]));
367	operands[1] = gen_rtx(CONST_INT, SImode,
368	CONST_DOUBLE_LOW(operands[1]));
369	}
370	else
371	if (GET_CODE (operands[1]) == CONST_INT)
372	{
373	lsw_operands[1] = operands[1];
374	operands[1] = const0_rtx;
375	}
376	else
377	abort();
378
379	if (GET_CODE (operands[2]) == REG)
380	lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1);
381	else
382	if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
383	lsw_operands[2] = adj_offsettable_operand(operands[2], 4);
384	else
385	if (GET_CODE (operands[2]) == CONST_DOUBLE)
386	{
387	lsw_operands[2] = gen_rtx(CONST_INT, SImode,
388	CONST_DOUBLE_HIGH(operands[2]));
389	operands[2] = gen_rtx(CONST_INT, SImode,
390	CONST_DOUBLE_LOW(operands[2]));
391	}
392	else
393	if (GET_CODE (operands[2]) == CONST_INT)
394	{
395	lsw_operands[2] = operands[2];
396	operands[2] = const0_rtx;
397	}
398	else
399	abort();
400
401	label[0] = gen_label_rtx();
402	LABEL_NUSES(label[0]) = 1;
403
404	output_asm_insn(\"subw3 %2, %1, %0\", operands);
405	output_asm_insn(\"subw3 %2, %1, %0\", lsw_operands);
406	output_asm_insn(\"BCCB %l0\", label);
407	output_asm_insn(\"DECW %0\", operands);
408	output_asm_insn(\"%l0:\", label);
409
410	return \"\";
411	}")
412
413	(define_insn ""
414	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
415	(minus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
416	(match_operand:SI 2 "general_operand" "mri")))]
417	""
418	"subw2 %2, %0")
419
420	(define_insn "subsi3"
421	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
422	(minus:SI (match_operand:SI 1 "general_operand" "mri")
423	(match_operand:SI 2 "general_operand" "mri")))]
424	""
425	"subw3 %2, %1, %0")
426
427	(define_insn ""
428	[(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
429	(minus:HI (match_operand:HI 1 "nonimmediate_operand" "0")
430	(match_operand:HI 2 "general_operand" "mri")))]
431	""
432	"subh2 %2, %0")
433
434	(define_insn "subhi3"
435	[(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
436	(minus:HI (match_operand:HI 1 "general_operand" "mri")
437	(match_operand:HI 2 "general_operand" "mri")))]
438	""
439	"subh3 %2, %1, %0")
440
441	(define_insn ""
442	[(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
443	(minus:QI (match_operand:QI 1 "nonimmediate_operand" "0")
444	(match_operand:QI 2 "general_operand" "mri")))]
445	""
446	"subb2 %2, %0")
447
448	(define_insn "subqi3"
449	[(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
450	(minus:QI (match_operand:QI 1 "general_operand" "mri")
451	(match_operand:QI 2 "general_operand" "mri")))]
452	""
453	"subb3 %2, %1, %0")
454
455	;; signed multiply instructions
456
457	(define_insn ""
458	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
459	(mult:SI (match_operand:SI 1 "nonimmediate_operand" "0")
460	(match_operand:SI 2 "general_operand" "mri")))]
461	""
462	"mulw2 %2, %0")
463
464	(define_insn "mulsi3"
465	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
466	(mult:SI (match_operand:SI 1 "general_operand" "mri")
467	(match_operand:SI 2 "general_operand" "mri")))]
468	""
469	"mulw3 %2, %1, %0")
470
471	;; signed divide instructions
472
473	(define_insn ""
474	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
475	(div:SI (match_operand:SI 1 "nonimmediate_operand" "0")
476	(match_operand:SI 2 "general_operand" "mri")))]
477	""
478	"divw2 %2, %0")
479
480	(define_insn "divsi3"
481	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
482	(div:SI (match_operand:SI 1 "general_operand" "mri")
483	(match_operand:SI 2 "general_operand" "mri")))]
484	""
485	"divw3 %2, %1, %0")
486
487	;; signed modulus instruction
488
489	(define_insn ""
490	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
491	(mod:SI (match_operand:SI 1 "nonimmediate_operand" "0")
492	(match_operand:SI 2 "general_operand" "mri")))]
493	""
494	"modw2 %2, %0")
495
496	(define_insn "modsi3"
497	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
498	(mod:SI (match_operand:SI 1 "general_operand" "mri")
499	(match_operand:SI 2 "general_operand" "mri")))]
500	""
501	"modw3 %2, %1, %0")
502
503	;; unsigned divide instruction
504
505	(define_insn ""
506	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
507	(udiv:SI (match_operand:SI 1 "nonimmediate_operand" "0")
508	(match_operand:SI 2 "general_operand" "mri")))]
509	""
510	"udivw2 %2, %0")
511
512	(define_insn "udivsi3"
513	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
514	(udiv:SI (match_operand:SI 1 "general_operand" "mri")
515	(match_operand:SI 2 "general_operand" "mri")))]
516	""
517	"udivw3 %2, %1, %0")
518
519	;; unsigned modulus instruction
520
521	(define_insn ""
522	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
523	(umod:SI (match_operand:SI 1 "nonimmediate_operand" "0")
524	(match_operand:SI 2 "general_operand" "mri")))]
525	""
526	"umodw2 %2, %0")
527
528	(define_insn "umodsi3"
529	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
530	(umod:SI (match_operand:SI 1 "general_operand" "mri")
531	(match_operand:SI 2 "general_operand" "mri")))]
532	""
533	"umodw3 %2, %1, %0")
534
535	;; logical-and instructions
536
537	(define_insn ""
538	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
539	(and:SI (match_operand:SI 1 "nonimmediate_operand" "0")
540	(match_operand:SI 2 "general_operand" "mri")))]
541	""
542	"andw2 %2, %0")
543
544	(define_insn "andsi3"
545	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
546	(and:SI (match_operand:SI 1 "general_operand" "mri")
547	(match_operand:SI 2 "general_operand" "mri")))]
548	""
549	"andw3 %2, %1, %0")
550
551	(define_insn ""
552	[(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
553	(and:HI (match_operand:HI 1 "nonimmediate_operand" "0")
554	(match_operand:HI 2 "general_operand" "mri")))]
555	""
556	"andh2 %2, %0")
557
558	(define_insn "andhi3"
559	[(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
560	(and:HI (match_operand:HI 1 "general_operand" "mri")
561	(match_operand:HI 2 "general_operand" "mri")))]
562	""
563	"andh3 %2, %1, %0")
564
565	(define_insn ""
566	[(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
567	(and:QI (match_operand:QI 1 "nonimmediate_operand" "0")
568	(match_operand:QI 2 "general_operand" "mri")))]
569	""
570	"andb2 %2, %0")
571
572	(define_insn "andqi3"
573	[(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
574	(and:QI (match_operand:QI 1 "general_operand" "mri")
575	(match_operand:QI 2 "general_operand" "mri")))]
576	""
577	"andb3 %2, %1, %0")
578
579	;; inclusive-or instructions
580
581	(define_insn ""
582	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
583	(ior:SI (match_operand:SI 1 "nonimmediate_operand" "0")
584	(match_operand:SI 2 "general_operand" "mri")))]
585	""
586	"orw2 %2, %0")
587
588	(define_insn "iorsi3"
589	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
590	(ior:SI (match_operand:SI 1 "general_operand" "mri")
591	(match_operand:SI 2 "general_operand" "mri")))]
592	""
593	"orw3 %2, %1, %0")
594
595	(define_insn ""
596	[(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
597	(ior:HI (match_operand:HI 1 "nonimmediate_operand" "0")
598	(match_operand:HI 2 "general_operand" "mri")))]
599	""
600	"orh2 %2, %0")
601
602	(define_insn "iorhi3"
603	[(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
604	(ior:HI (match_operand:HI 1 "general_operand" "mri")
605	(match_operand:HI 2 "general_operand" "mri")))]
606	""
607	"orh3 %2, %1, %0")
608
609	(define_insn ""
610	[(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
611	(ior:QI (match_operand:QI 1 "nonimmediate_operand" "0")
612	(match_operand:QI 2 "general_operand" "mri")))]
613	""
614	"orb2 %2, %0")
615
616	(define_insn "iorqi3"
617	[(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
618	(ior:QI (match_operand:QI 1 "general_operand" "mri")
619	(match_operand:QI 2 "general_operand" "mri")))]
620	""
621	"orb3 %2, %1, %0")
622
623	;; exclusive-or instructions
624
625	(define_insn ""
626	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
627	(xor:SI (match_operand:SI 1 "nonimmediate_operand" "0")
628	(match_operand:SI 2 "general_operand" "mri")))]
629	""
630	"xorw2 %2, %0")
631
632	(define_insn "xorsi3"
633	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
634	(xor:SI (match_operand:SI 1 "general_operand" "mri")
635	(match_operand:SI 2 "general_operand" "mri")))]
636	""
637	"xorw3 %2, %1, %0")
638
639	(define_insn ""
640	[(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
641	(xor:HI (match_operand:HI 1 "nonimmediate_operand" "0")
642	(match_operand:HI 2 "general_operand" "mri")))]
643	""
644	"xorh2 %2, %0")
645
646	(define_insn "xorhi3"
647	[(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
648	(xor:HI (match_operand:HI 1 "general_operand" "mri")
649	(match_operand:HI 2 "general_operand" "mri")))]
650	""
651	"xorh3 %2, %1, %0")
652
653	(define_insn ""
654	[(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
655	(xor:QI (match_operand:QI 1 "nonimmediate_operand" "0")
656	(match_operand:QI 2 "general_operand" "mri")))]
657	""
658	"xorb2 %2, %0")
659
660	(define_insn "xorqi3"
661	[(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
662	(xor:QI (match_operand:QI 1 "general_operand" "mri")
663	(match_operand:QI 2 "general_operand" "mri")))]
664	""
665	"xorb3 %2, %1, %0")
666
667	;; arithmetic shift instructions
668
669	(define_insn "ashlsi3"
670	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
671	(ashift:SI (match_operand:SI 1 "general_operand" "mri")
672	(match_operand:SI 2 "general_operand" "mri")))]
673	""
674	"LLSW3 %2, %1, %0")
675
676	(define_insn "ashrsi3"
677	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
678	(ashiftrt:SI (match_operand:SI 1 "general_operand" "mri")
679	(match_operand:SI 2 "general_operand" "mri")))]
680	""
681	"ARSW3 %2, %1, %0")
682
683	;; logical shift instructions
684
685	(define_insn "lshrsi3"
686	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
687	(lshiftrt:SI (match_operand:SI 1 "general_operand" "mri")
688	(match_operand:SI 2 "general_operand" "mri")))]
689	""
690	"LRSW3 %2, %1, %0")
691
692	;; rotate instruction
693
694	(define_insn "rotrsi3"
695	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
696	(rotatert: SI (match_operand:SI 1 "general_operand" "mri")
697	(match_operand:SI 2 "general_operand" "mri")))]
698	""
699	"ROTW %2, %1, %0")
700
701	;; negate instructions
702
703	(define_insn "negsi2"
704	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
705	(neg:SI (match_operand:SI 1 "general_operand" "mri")))]
706	""
707	"mnegw %1, %0")
708
709	(define_insn "neghi2"
710	[(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
711	(neg:HI (match_operand:HI 1 "general_operand" "mri")))]
712	""
713	"mnegh %1, %0")
714
715	;; complement instructions
716
717	(define_insn "one_cmplsi2"
718	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
719	(not:SI (match_operand:SI 1 "general_operand" "mri")))]
720	""
721	"mcomw %1, %0")
722
723	(define_insn "one_cmplhi2"
724	[(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
725	(not:HI (match_operand:HI 1 "general_operand" "mri")))]
726	""
727	"mcomh %1, %0")
728
729	(define_insn "one_cmplqi2"
730	[(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
731	(not:QI (match_operand:QI 1 "general_operand" "mri")))]
732	""
733	"mcomb %1, %0")
734
735	;; test instruction
736
737	;; We don't want to allow a constant operand for test insns because
738	;; (set (cc0) (const_int foo)) has no mode information. Such insns will
739	;; be folded while optimizing anyway.
740
741	(define_insn "tstsi"
742	[(set (cc0) (match_operand:SI 0 "nonimmediate_operand" "mr"))]
743	""
744	"TSTW %0")
745
746	(define_insn "tsthi"
747	[(set (cc0) (match_operand:HI 0 "nonimmediate_operand" "mr"))]
748	""
749	"TSTH %0")
750
751	(define_insn "tstqi"
752	[(set (cc0) (match_operand:QI 0 "nonimmediate_operand" "mr"))]
753	""
754	"TSTB {sbyte}%0")
755
756	;; compare instruction
757
758	(define_insn "cmpsi"
759	[(set (cc0) (compare (match_operand:SI 0 "nonimmediate_operand" "mr")
760	(match_operand:SI 1 "general_operand" "mri")))]
761	""
762	"CMPW %1, %0")
763
764	(define_insn "cmphi"
765	[(set (cc0) (compare (match_operand:HI 0 "nonimmediate_operand" "mr")
766	(match_operand:HI 1 "general_operand" "mri")))]
767	""
768	"*
769	{
770
771	if (GET_CODE (operands[1]) == CONST_INT &&
772	((unsigned long)INTVAL (operands[1]) & 0x8000L))
773	operands[1] = gen_rtx(CONST_INT, SImode, INTVAL(operands[1]) \| 0xffff0000L);
774
775	output_asm_insn(\"CMPH %1, %0\",operands);
776
777	return \"\";
778	}")
779
780	(define_insn "cmpqi"
781	[(set (cc0) (compare (match_operand:QI 0 "nonimmediate_operand" "mr")
782	(match_operand:QI 1 "general_operand" "mri")))]
783	""
784	"*
785	{
786
787	if (GET_CODE (operands[1]) == CONST_INT &&
788	((unsigned long)INTVAL (operands[1]) & 0x80L))
789	operands[1] = gen_rtx(CONST_INT, SImode, INTVAL(operands[1]) \| 0xffffff00L);
790
791	output_asm_insn(\"CMPB {sbyte}%1, {sbyte}%0\",operands);
792
793	return \"\";
794	}")
795
796	;; truncate instructions
797
798	(define_insn ""
799	[(set (match_operand:SF 0 "register_operand" "=r")
800	(float_truncate:SF (match_operand:DF 1 "general_operand" "orF")))
801	(clobber (reg:SI 1))
802	(clobber (reg:SI 2))]
803	"REGNO (operands[0]) == 0"
804	"*
805	{
806	output_push_double(&operands[1]);
807	output_asm_insn(\"call &2, _fdtos\", operands);
808
809	return \"\";
810	}")
811
812	(define_expand "truncdfsf2"
813	[(parallel [(set (reg:SF 0)
814	(float_truncate:SF (match_operand:DF 1 "general_operand" "orF")))
815	(clobber (reg:SI 1))
816	(clobber (reg:SI 2))])
817	(set (match_operand:SF 0 "nonimmediate_operand" "=mr")
818	(reg:SF 0))]
819	""
820	"")
821
822	(define_insn "truncsihi2"
823	[(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
824	(truncate:HI (match_operand:SI 1 "general_operand" "mri")))]
825	""
826	"movtwh %1, %0")
827
828	(define_insn "truncsiqi2"
829	[(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
830	(truncate:QI (match_operand:SI 1 "general_operand" "mri")))]
831	""
832	"movtwb %1, %0")
833
834	(define_insn "trunchiqi2"
835	[(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
836	(truncate:QI (match_operand:HI 1 "general_operand" "mri")))]
837	""
838	"movthb %1, %0")
839
840	;; sign-extend move instructions
841
842	(define_insn ""
843	[(set (match_operand:DF 0 "register_operand" "=r")
844	(float_extend:DF (match_operand:SF 1 "general_operand" "mrF")))
845	(clobber (reg:SI 2))]
846	"REGNO (operands[0]) == 0"
847	"*
848	{
849	output_asm_insn(\"pushw %1\", operands);
850	output_asm_insn(\"call &1, _fstod\", operands);
851
852	return \"\";
853	}")
854
855	(define_expand "extendsfdf2"
856	[(parallel [(set (reg:DF 0)
857	(float_extend:DF (match_operand:SF 1 "general_operand" "mrF")))
858	(clobber (reg:SI 2))])
859	(set (match_operand:DF 0 "nonimmediate_operand" "=or")
860	(reg:DF 0))]
861	""
862	"")
863
864	(define_insn "extendhisi2"
865	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
866	(sign_extend:SI (match_operand:HI 1 "general_operand" "mri")))]
867	""
868	"movbhw %1, %0")
869
870	(define_insn "extendqisi2"
871	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
872	(sign_extend:SI (match_operand:QI 1 "general_operand" "mri")))]
873	""
874	"movbbw %1, %0")
875
876	(define_insn "extendqihi2"
877	[(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
878	(sign_extend:HI (match_operand:QI 1 "general_operand" "mri")))]
879	""
880	"movbbh %1, %0")
881
882	;; zero-extend move instructions
883
884	(define_insn "zero_extendhisi2"
885	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
886	(zero_extend:SI (match_operand:HI 1 "general_operand" "mri")))]
887	""
888	"movzhw %1, %0")
889
890	(define_insn "zero_extendqisi2"
891	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
892	(zero_extend:SI (match_operand:QI 1 "general_operand" "mri")))]
893	""
894	"movzbw %1, %0")
895
896	(define_insn "zero_extendqihi2"
897	[(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
898	(zero_extend:HI (match_operand:QI 1 "general_operand" "mri")))]
899	""
900	"movzbh %1, %0")
901
902	;; bit field instructions
903
904	(define_insn "extzv"
905	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
906	(zero_extract:SI (match_operand:SI 1 "general_operand" "mri")
907	(match_operand:SI 2 "immediate_operand" "i")
908	(match_operand:SI 3 "general_operand" "mri")))]
909	""
910	"*
911	{
912
913	operands[2] = gen_rtx(CONST_INT, SImode, INTVAL(operands[2]) - 1);
914	output_asm_insn(\"EXTFW %2, %3, %1, %0\",operands);
915
916	return \"\";
917	}")
918
919	(define_insn ""
920	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
921	(zero_extract:SI (match_operand:HI 1 "general_operand" "mri")
922	(match_operand:SI 2 "immediate_operand" "i")
923	(match_operand:SI 3 "general_operand" "mri")))]
924	""
925	"*
926	{
927
928	operands[2] = gen_rtx(CONST_INT, SImode, INTVAL(operands[2]) - 1);
929	output_asm_insn(\"EXTFH %2, %3, {uhalf}%1, {uword}%0\",operands);
930
931	return \"\";
932	}")
933
934	(define_insn ""
935	[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
936	(zero_extract:SI (match_operand:QI 1 "general_operand" "mri")
937	(match_operand:SI 2 "immediate_operand" "i")
938	(match_operand:SI 3 "general_operand" "mri")))]
939	""
940	"*
941	{
942
943	operands[2] = gen_rtx(CONST_INT, SImode, INTVAL(operands[2]) - 1);
944	output_asm_insn(\"EXTFB %2, %3, {ubyte}%1, {uword}%0\",operands);
945
946	return \"\";
947	}")
948
949	(define_insn "insv"
950	[(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+mr")
951	(match_operand:SI 1 "immediate_operand" "i")
952	(match_operand:SI 2 "general_operand" "mri"))
953	(match_operand:SI 3 "general_operand" "mri"))]
954	""
955	"*
956	{
957
958	operands[1] = gen_rtx(CONST_INT, SImode, INTVAL(operands[1]) - 1);
959	output_asm_insn(\"INSFW %1, %2, %3, %0\",operands);
960
961	return \"\";
962	}")
963
964	(define_insn ""
965	[(set (zero_extract:SI (match_operand:HI 0 "nonimmediate_operand" "+mr")
966	(match_operand:SI 1 "immediate_operand" "i")
967	(match_operand:SI 2 "general_operand" "mri"))
968	(match_operand:SI 3 "general_operand" "mri"))]
969	""
970	"*
971	{
972
973	operands[1] = gen_rtx(CONST_INT, SImode, INTVAL(operands[1]) - 1);
974	output_asm_insn(\"INSFH %1, %2, {uword}%3, {uhalf}%0\",operands);
975
976	return \"\";
977	}")
978
979	(define_insn ""
980	[(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+mr")
981	(match_operand:SI 1 "immediate_operand" "i")
982	(match_operand:SI 2 "general_operand" "mri"))
983	(match_operand:SI 3 "general_operand" "mri"))]
984	""
985	"*
986	{
987
988	operands[1] = gen_rtx(CONST_INT, SImode, INTVAL(operands[1]) - 1);
989	output_asm_insn(\"INSFB %1, %2, {uword}%3, {ubyte}%0\",operands);
990
991	return \"\";
992	}")
993
994	;; conditional branch instructions
995
996	(define_insn "beq"
997	[(set (pc) (if_then_else (eq (cc0) (const_int 0))
998	(label_ref (match_operand 0 "" ""))
999	(pc)))]
1000	""
1001	"je %l0")
1002
1003	(define_insn "bne"
1004	[(set (pc) (if_then_else (ne (cc0) (const_int 0))
1005	(label_ref (match_operand 0 "" ""))
1006	(pc)))]
1007	""
1008	"jne %l0")
1009
1010	(define_insn "bgt"
1011	[(set (pc) (if_then_else (gt (cc0) (const_int 0))
1012	(label_ref (match_operand 0 "" ""))
1013	(pc)))]
1014	""
1015	"jg %l0")
1016
1017	(define_insn "bgtu"
1018	[(set (pc) (if_then_else (gtu (cc0) (const_int 0))
1019	(label_ref (match_operand 0 "" ""))
1020	(pc)))]
1021	""
1022	"jgu %l0")
1023
1024	(define_insn "blt"
1025	[(set (pc) (if_then_else (lt (cc0) (const_int 0))
1026	(label_ref (match_operand 0 "" ""))
1027	(pc)))]
1028	""
1029	"jl %l0")
1030
1031	(define_insn "bltu"
1032	[(set (pc) (if_then_else (ltu (cc0) (const_int 0))
1033	(label_ref (match_operand 0 "" ""))
1034	(pc)))]
1035	""
1036	"jlu %l0")
1037
1038	(define_insn "bge"
1039	[(set (pc) (if_then_else (ge (cc0) (const_int 0))
1040	(label_ref (match_operand 0 "" ""))
1041	(pc)))]
1042	""
1043	"jge %l0")
1044
1045	(define_insn "bgeu"
1046	[(set (pc) (if_then_else (geu (cc0) (const_int 0))
1047	(label_ref (match_operand 0 "" ""))
1048	(pc)))]
1049	""
1050	"jgeu %l0")
1051
1052	(define_insn "ble"
1053	[(set (pc) (if_then_else (le (cc0) (const_int 0))
1054	(label_ref (match_operand 0 "" ""))
1055	(pc)))]
1056	""
1057	"jle %l0")
1058
1059	(define_insn "bleu"
1060	[(set (pc) (if_then_else (leu (cc0) (const_int 0))
1061	(label_ref (match_operand 0 "" ""))
1062	(pc)))]
1063	""
1064	"jleu %l0")
1065
1066	;; reverse-conditional branch instructions
1067
1068	(define_insn ""
1069	[(set (pc) (if_then_else (eq (cc0) (const_int 0))
1070	(pc)
1071	(label_ref (match_operand 0 "" ""))))]
1072	""
1073	"jne %l0")
1074
1075	(define_insn ""
1076	[(set (pc) (if_then_else (ne (cc0) (const_int 0))
1077	(pc)
1078	(label_ref (match_operand 0 "" ""))))]
1079	""
1080	"je %l0")
1081
1082	(define_insn ""
1083	[(set (pc) (if_then_else (gt (cc0) (const_int 0))
1084	(pc)
1085	(label_ref (match_operand 0 "" ""))))]
1086	""
1087	"jle %l0")
1088
1089	(define_insn ""
1090	[(set (pc) (if_then_else (gtu (cc0) (const_int 0))
1091	(pc)
1092	(label_ref (match_operand 0 "" ""))))]
1093	""
1094	"jleu %l0")
1095
1096	(define_insn ""
1097	[(set (pc) (if_then_else (lt (cc0) (const_int 0))
1098	(pc)
1099	(label_ref (match_operand 0 "" ""))))]
1100	""
1101	"jge %l0")
1102
1103	(define_insn ""
1104	[(set (pc) (if_then_else (ltu (cc0) (const_int 0))
1105	(pc)
1106	(label_ref (match_operand 0 "" ""))))]
1107	""
1108	"jgeu %l0")
1109
1110	(define_insn ""
1111	[(set (pc) (if_then_else (ge (cc0) (const_int 0))
1112	(pc)
1113	(label_ref (match_operand 0 "" ""))))]
1114	""
1115	"jl %l0")
1116
1117	(define_insn ""
1118	[(set (pc) (if_then_else (geu (cc0) (const_int 0))
1119	(pc)
1120	(label_ref (match_operand 0 "" ""))))]
1121	""
1122	"jlu %l0")
1123
1124	(define_insn ""
1125	[(set (pc) (if_then_else (le (cc0) (const_int 0))
1126	(pc)
1127	(label_ref (match_operand 0 "" ""))))]
1128	""
1129	"jg %l0")
1130
1131	(define_insn ""
1132	[(set (pc) (if_then_else (leu (cc0) (const_int 0))
1133	(pc)
1134	(label_ref (match_operand 0 "" ""))))]
1135	""
1136	"jgu %l0")
1137
1138	;; call instructions
1139
1140	(define_insn "call"
1141	[(call (match_operand:QI 0 "memory_operand" "m")
1142	(match_operand:SI 1 "immediate_operand" "i"))]
1143	""
1144	"call %1/4, %0")
1145
1146	(define_insn "call_value"
1147	[(set (match_operand 0 "register_operand" "=r")
1148	(call (match_operand:QI 1 "memory_operand" "m")
1149	(match_operand:SI 2 "immediate_operand" "i")))]
1150	""
1151	"call %2/4, %1")
1152
1153	;; No-op instruction
1154
1155	(define_insn "nop"
1156	[(const_int 0)]
1157	""
1158	"NOP")
1159
1160	;; jump through a dispatch table instruction
1161
1162	(define_expand "casesi"
1163	[(use (match_operand:SI 0 "general_operand" "mri"))
1164	(set (cc0) (compare (match_dup 5)
1165	(match_operand:SI 1 "general_operand" "mri")))
1166	(set (pc) (if_then_else (lt (cc0) (const_int 0))
1167	(label_ref (match_operand 4 "" ""))
1168	(pc)))
1169	(set (match_dup 5) (minus:SI (match_dup 5)
1170	(match_dup 1)))
1171	(set (cc0) (compare (match_dup 5)
1172	(match_operand:SI 2 "general_operand" "mri")))
1173	(set (pc) (if_then_else (gtu (cc0) (const_int 0))
1174	(label_ref (match_dup 4))
1175	(pc)))
1176	(set (match_dup 5) (ashift:SI (match_dup 5)
1177	(const_int 2)))
1178	(set (pc) (mem:SI (plus:SI (label_ref (match_operand 3 "" ""))
1179	(match_dup 5))))]
1180	""
1181	"
1182	{
1183	operands[5] = gen_reg_rtx(GET_MODE (operands[0]));
1184	emit_move_insn(operands[5], operands[0]);
1185	}")
1186
1187	;; jump instructions
1188
1189	(define_insn "indirect_jump"
1190	[(set (pc) (match_operand:SI 0 "address_operand" "p"))]
1191	""
1192	"jmp %a0")
1193
1194	(define_insn "jump"
1195	[(set (pc) (label_ref (match_operand 0 "" "")))]
1196	""
1197	"jmp %l0")

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