1 | This is Info file gcc.info, produced by Makeinfo version 1.67 from the |
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2 | input file gcc.texi. |
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3 | |
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4 | This file documents the use and the internals of the GNU compiler. |
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5 | |
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6 | Published by the Free Software Foundation 59 Temple Place - Suite 330 |
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7 | Boston, MA 02111-1307 USA |
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8 | |
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9 | Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998 |
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10 | Free Software Foundation, Inc. |
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11 | |
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12 | Permission is granted to make and distribute verbatim copies of this |
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13 | manual provided the copyright notice and this permission notice are |
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14 | preserved on all copies. |
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15 | |
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16 | Permission is granted to copy and distribute modified versions of |
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17 | this manual under the conditions for verbatim copying, provided also |
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18 | that the sections entitled "GNU General Public License," "Funding for |
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19 | Free Software," and "Protect Your Freedom--Fight `Look And Feel'" are |
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20 | included exactly as in the original, and provided that the entire |
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21 | resulting derived work is distributed under the terms of a permission |
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22 | notice identical to this one. |
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23 | |
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24 | Permission is granted to copy and distribute translations of this |
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25 | manual into another language, under the above conditions for modified |
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26 | versions, except that the sections entitled "GNU General Public |
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27 | License," "Funding for Free Software," and "Protect Your Freedom--Fight |
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28 | `Look And Feel'", and this permission notice, may be included in |
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29 | translations approved by the Free Software Foundation instead of in the |
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30 | original English. |
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31 | |
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32 | |
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33 | File: gcc.info, Node: Regs and Memory, Next: Arithmetic, Prev: Constants, Up: RTL |
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34 | |
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35 | Registers and Memory |
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36 | ==================== |
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37 | |
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38 | Here are the RTL expression types for describing access to machine |
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39 | registers and to main memory. |
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40 | |
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41 | `(reg:M N)' |
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42 | For small values of the integer N (those that are less than |
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43 | `FIRST_PSEUDO_REGISTER'), this stands for a reference to machine |
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44 | register number N: a "hard register". For larger values of N, it |
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45 | stands for a temporary value or "pseudo register". The compiler's |
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46 | strategy is to generate code assuming an unlimited number of such |
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47 | pseudo registers, and later convert them into hard registers or |
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48 | into memory references. |
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49 | |
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50 | M is the machine mode of the reference. It is necessary because |
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51 | machines can generally refer to each register in more than one |
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52 | mode. For example, a register may contain a full word but there |
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53 | may be instructions to refer to it as a half word or as a single |
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54 | byte, as well as instructions to refer to it as a floating point |
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55 | number of various precisions. |
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56 | |
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57 | Even for a register that the machine can access in only one mode, |
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58 | the mode must always be specified. |
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59 | |
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60 | The symbol `FIRST_PSEUDO_REGISTER' is defined by the machine |
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61 | description, since the number of hard registers on the machine is |
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62 | an invariant characteristic of the machine. Note, however, that |
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63 | not all of the machine registers must be general registers. All |
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64 | the machine registers that can be used for storage of data are |
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65 | given hard register numbers, even those that can be used only in |
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66 | certain instructions or can hold only certain types of data. |
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67 | |
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68 | A hard register may be accessed in various modes throughout one |
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69 | function, but each pseudo register is given a natural mode and is |
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70 | accessed only in that mode. When it is necessary to describe an |
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71 | access to a pseudo register using a nonnatural mode, a `subreg' |
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72 | expression is used. |
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73 | |
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74 | A `reg' expression with a machine mode that specifies more than |
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75 | one word of data may actually stand for several consecutive |
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76 | registers. If in addition the register number specifies a |
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77 | hardware register, then it actually represents several consecutive |
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78 | hardware registers starting with the specified one. |
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79 | |
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80 | Each pseudo register number used in a function's RTL code is |
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81 | represented by a unique `reg' expression. |
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82 | |
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83 | Some pseudo register numbers, those within the range of |
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84 | `FIRST_VIRTUAL_REGISTER' to `LAST_VIRTUAL_REGISTER' only appear |
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85 | during the RTL generation phase and are eliminated before the |
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86 | optimization phases. These represent locations in the stack frame |
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87 | that cannot be determined until RTL generation for the function |
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88 | has been completed. The following virtual register numbers are |
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89 | defined: |
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90 | |
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91 | `VIRTUAL_INCOMING_ARGS_REGNUM' |
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92 | This points to the first word of the incoming arguments |
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93 | passed on the stack. Normally these arguments are placed |
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94 | there by the caller, but the callee may have pushed some |
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95 | arguments that were previously passed in registers. |
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96 | |
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97 | When RTL generation is complete, this virtual register is |
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98 | replaced by the sum of the register given by |
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99 | `ARG_POINTER_REGNUM' and the value of `FIRST_PARM_OFFSET'. |
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100 | |
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101 | `VIRTUAL_STACK_VARS_REGNUM' |
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102 | If `FRAME_GROWS_DOWNWARD' is defined, this points to |
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103 | immediately above the first variable on the stack. |
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104 | Otherwise, it points to the first variable on the stack. |
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105 | |
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106 | `VIRTUAL_STACK_VARS_REGNUM' is replaced with the sum of the |
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107 | register given by `FRAME_POINTER_REGNUM' and the value |
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108 | `STARTING_FRAME_OFFSET'. |
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109 | |
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110 | `VIRTUAL_STACK_DYNAMIC_REGNUM' |
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111 | This points to the location of dynamically allocated memory |
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112 | on the stack immediately after the stack pointer has been |
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113 | adjusted by the amount of memory desired. |
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114 | |
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115 | This virtual register is replaced by the sum of the register |
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116 | given by `STACK_POINTER_REGNUM' and the value |
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117 | `STACK_DYNAMIC_OFFSET'. |
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118 | |
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119 | `VIRTUAL_OUTGOING_ARGS_REGNUM' |
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120 | This points to the location in the stack at which outgoing |
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121 | arguments should be written when the stack is pre-pushed |
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122 | (arguments pushed using push insns should always use |
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123 | `STACK_POINTER_REGNUM'). |
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124 | |
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125 | This virtual register is replaced by the sum of the register |
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126 | given by `STACK_POINTER_REGNUM' and the value |
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127 | `STACK_POINTER_OFFSET'. |
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128 | |
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129 | `(subreg:M REG WORDNUM)' |
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130 | `subreg' expressions are used to refer to a register in a machine |
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131 | mode other than its natural one, or to refer to one register of a |
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132 | multi-word `reg' that actually refers to several registers. |
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133 | |
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134 | Each pseudo-register has a natural mode. If it is necessary to |
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135 | operate on it in a different mode--for example, to perform a |
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136 | fullword move instruction on a pseudo-register that contains a |
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137 | single byte--the pseudo-register must be enclosed in a `subreg'. |
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138 | In such a case, WORDNUM is zero. |
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139 | |
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140 | Usually M is at least as narrow as the mode of REG, in which case |
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141 | it is restricting consideration to only the bits of REG that are |
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142 | in M. |
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143 | |
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144 | Sometimes M is wider than the mode of REG. These `subreg' |
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145 | expressions are often called "paradoxical". They are used in |
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146 | cases where we want to refer to an object in a wider mode but do |
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147 | not care what value the additional bits have. The reload pass |
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148 | ensures that paradoxical references are only made to hard |
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149 | registers. |
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150 | |
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151 | The other use of `subreg' is to extract the individual registers of |
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152 | a multi-register value. Machine modes such as `DImode' and |
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153 | `TImode' can indicate values longer than a word, values which |
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154 | usually require two or more consecutive registers. To access one |
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155 | of the registers, use a `subreg' with mode `SImode' and a WORDNUM |
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156 | that says which register. |
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157 | |
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158 | Storing in a non-paradoxical `subreg' has undefined results for |
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159 | bits belonging to the same word as the `subreg'. This laxity makes |
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160 | it easier to generate efficient code for such instructions. To |
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161 | represent an instruction that preserves all the bits outside of |
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162 | those in the `subreg', use `strict_low_part' around the `subreg'. |
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163 | |
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164 | The compilation parameter `WORDS_BIG_ENDIAN', if set to 1, says |
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165 | that word number zero is the most significant part; otherwise, it |
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166 | is the least significant part. |
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167 | |
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168 | Between the combiner pass and the reload pass, it is possible to |
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169 | have a paradoxical `subreg' which contains a `mem' instead of a |
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170 | `reg' as its first operand. After the reload pass, it is also |
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171 | possible to have a non-paradoxical `subreg' which contains a |
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172 | `mem'; this usually occurs when the `mem' is a stack slot which |
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173 | replaced a pseudo register. |
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174 | |
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175 | Note that it is not valid to access a `DFmode' value in `SFmode' |
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176 | using a `subreg'. On some machines the most significant part of a |
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177 | `DFmode' value does not have the same format as a single-precision |
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178 | floating value. |
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179 | |
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180 | It is also not valid to access a single word of a multi-word value |
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181 | in a hard register when less registers can hold the value than |
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182 | would be expected from its size. For example, some 32-bit |
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183 | machines have floating-point registers that can hold an entire |
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184 | `DFmode' value. If register 10 were such a register `(subreg:SI |
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185 | (reg:DF 10) 1)' would be invalid because there is no way to |
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186 | convert that reference to a single machine register. The reload |
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187 | pass prevents `subreg' expressions such as these from being formed. |
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188 | |
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189 | The first operand of a `subreg' expression is customarily accessed |
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190 | with the `SUBREG_REG' macro and the second operand is customarily |
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191 | accessed with the `SUBREG_WORD' macro. |
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192 | |
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193 | `(scratch:M)' |
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194 | This represents a scratch register that will be required for the |
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195 | execution of a single instruction and not used subsequently. It is |
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196 | converted into a `reg' by either the local register allocator or |
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197 | the reload pass. |
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198 | |
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199 | `scratch' is usually present inside a `clobber' operation (*note |
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200 | Side Effects::.). |
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201 | |
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202 | `(cc0)' |
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203 | This refers to the machine's condition code register. It has no |
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204 | operands and may not have a machine mode. There are two ways to |
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205 | use it: |
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206 | |
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207 | * To stand for a complete set of condition code flags. This is |
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208 | best on most machines, where each comparison sets the entire |
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209 | series of flags. |
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210 | |
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211 | With this technique, `(cc0)' may be validly used in only two |
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212 | contexts: as the destination of an assignment (in test and |
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213 | compare instructions) and in comparison operators comparing |
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214 | against zero (`const_int' with value zero; that is to say, |
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215 | `const0_rtx'). |
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216 | |
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217 | * To stand for a single flag that is the result of a single |
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218 | condition. This is useful on machines that have only a |
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219 | single flag bit, and in which comparison instructions must |
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220 | specify the condition to test. |
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221 | |
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222 | With this technique, `(cc0)' may be validly used in only two |
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223 | contexts: as the destination of an assignment (in test and |
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224 | compare instructions) where the source is a comparison |
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225 | operator, and as the first operand of `if_then_else' (in a |
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226 | conditional branch). |
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227 | |
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228 | There is only one expression object of code `cc0'; it is the value |
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229 | of the variable `cc0_rtx'. Any attempt to create an expression of |
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230 | code `cc0' will return `cc0_rtx'. |
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231 | |
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232 | Instructions can set the condition code implicitly. On many |
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233 | machines, nearly all instructions set the condition code based on |
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234 | the value that they compute or store. It is not necessary to |
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235 | record these actions explicitly in the RTL because the machine |
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236 | description includes a prescription for recognizing the |
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237 | instructions that do so (by means of the macro |
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238 | `NOTICE_UPDATE_CC'). *Note Condition Code::. Only instructions |
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239 | whose sole purpose is to set the condition code, and instructions |
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240 | that use the condition code, need mention `(cc0)'. |
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241 | |
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242 | On some machines, the condition code register is given a register |
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243 | number and a `reg' is used instead of `(cc0)'. This is usually the |
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244 | preferable approach if only a small subset of instructions modify |
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245 | the condition code. Other machines store condition codes in |
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246 | general registers; in such cases a pseudo register should be used. |
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247 | |
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248 | Some machines, such as the Sparc and RS/6000, have two sets of |
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249 | arithmetic instructions, one that sets and one that does not set |
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250 | the condition code. This is best handled by normally generating |
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251 | the instruction that does not set the condition code, and making a |
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252 | pattern that both performs the arithmetic and sets the condition |
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253 | code register (which would not be `(cc0)' in this case). For |
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254 | examples, search for `addcc' and `andcc' in `sparc.md'. |
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255 | |
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256 | `(pc)' |
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257 | This represents the machine's program counter. It has no operands |
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258 | and may not have a machine mode. `(pc)' may be validly used only |
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259 | in certain specific contexts in jump instructions. |
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260 | |
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261 | There is only one expression object of code `pc'; it is the value |
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262 | of the variable `pc_rtx'. Any attempt to create an expression of |
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263 | code `pc' will return `pc_rtx'. |
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264 | |
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265 | All instructions that do not jump alter the program counter |
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266 | implicitly by incrementing it, but there is no need to mention |
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267 | this in the RTL. |
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268 | |
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269 | `(mem:M ADDR)' |
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270 | This RTX represents a reference to main memory at an address |
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271 | represented by the expression ADDR. M specifies how large a unit |
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272 | of memory is accessed. |
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273 | |
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274 | `(addressof:M REG)' |
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275 | This RTX represents a request for the address of register REG. |
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276 | Its mode is always `Pmode'. If there are any `addressof' |
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277 | expressions left in the function after CSE, REG is forced into the |
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278 | stack and the `addressof' expression is replaced with a `plus' |
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279 | expression for the address of its stack slot. |
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280 | |
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281 | |
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282 | File: gcc.info, Node: Arithmetic, Next: Comparisons, Prev: Regs and Memory, Up: RTL |
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283 | |
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284 | RTL Expressions for Arithmetic |
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285 | ============================== |
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286 | |
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287 | Unless otherwise specified, all the operands of arithmetic |
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288 | expressions must be valid for mode M. An operand is valid for mode M |
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289 | if it has mode M, or if it is a `const_int' or `const_double' and M is |
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290 | a mode of class `MODE_INT'. |
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291 | |
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292 | For commutative binary operations, constants should be placed in the |
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293 | second operand. |
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294 | |
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295 | `(plus:M X Y)' |
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296 | Represents the sum of the values represented by X and Y carried |
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297 | out in machine mode M. |
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298 | |
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299 | `(lo_sum:M X Y)' |
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300 | Like `plus', except that it represents that sum of X and the |
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301 | low-order bits of Y. The number of low order bits is |
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302 | machine-dependent but is normally the number of bits in a `Pmode' |
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303 | item minus the number of bits set by the `high' code (*note |
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304 | Constants::.). |
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305 | |
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306 | M should be `Pmode'. |
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307 | |
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308 | `(minus:M X Y)' |
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309 | Like `plus' but represents subtraction. |
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310 | |
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311 | `(compare:M X Y)' |
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312 | Represents the result of subtracting Y from X for purposes of |
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313 | comparison. The result is computed without overflow, as if with |
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314 | infinite precision. |
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315 | |
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316 | Of course, machines can't really subtract with infinite precision. |
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317 | However, they can pretend to do so when only the sign of the |
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318 | result will be used, which is the case when the result is stored |
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319 | in the condition code. And that is the only way this kind of |
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320 | expression may validly be used: as a value to be stored in the |
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321 | condition codes. |
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322 | |
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323 | The mode M is not related to the modes of X and Y, but instead is |
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324 | the mode of the condition code value. If `(cc0)' is used, it is |
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325 | `VOIDmode'. Otherwise it is some mode in class `MODE_CC', often |
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326 | `CCmode'. *Note Condition Code::. |
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327 | |
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328 | Normally, X and Y must have the same mode. Otherwise, `compare' |
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329 | is valid only if the mode of X is in class `MODE_INT' and Y is a |
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330 | `const_int' or `const_double' with mode `VOIDmode'. The mode of X |
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331 | determines what mode the comparison is to be done in; thus it must |
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332 | not be `VOIDmode'. |
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333 | |
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334 | If one of the operands is a constant, it should be placed in the |
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335 | second operand and the comparison code adjusted as appropriate. |
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336 | |
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337 | A `compare' specifying two `VOIDmode' constants is not valid since |
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338 | there is no way to know in what mode the comparison is to be |
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339 | performed; the comparison must either be folded during the |
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340 | compilation or the first operand must be loaded into a register |
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341 | while its mode is still known. |
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342 | |
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343 | `(neg:M X)' |
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344 | Represents the negation (subtraction from zero) of the value |
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345 | represented by X, carried out in mode M. |
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346 | |
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347 | `(mult:M X Y)' |
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348 | Represents the signed product of the values represented by X and Y |
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349 | carried out in machine mode M. |
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350 | |
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351 | Some machines support a multiplication that generates a product |
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352 | wider than the operands. Write the pattern for this as |
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353 | |
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354 | (mult:M (sign_extend:M X) (sign_extend:M Y)) |
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355 | |
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356 | where M is wider than the modes of X and Y, which need not be the |
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357 | same. |
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358 | |
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359 | Write patterns for unsigned widening multiplication similarly using |
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360 | `zero_extend'. |
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361 | |
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362 | `(div:M X Y)' |
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363 | Represents the quotient in signed division of X by Y, carried out |
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364 | in machine mode M. If M is a floating point mode, it represents |
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365 | the exact quotient; otherwise, the integerized quotient. |
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366 | |
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367 | Some machines have division instructions in which the operands and |
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368 | quotient widths are not all the same; you should represent such |
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369 | instructions using `truncate' and `sign_extend' as in, |
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370 | |
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371 | (truncate:M1 (div:M2 X (sign_extend:M2 Y))) |
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372 | |
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373 | `(udiv:M X Y)' |
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374 | Like `div' but represents unsigned division. |
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375 | |
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376 | `(mod:M X Y)' |
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377 | `(umod:M X Y)' |
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378 | Like `div' and `udiv' but represent the remainder instead of the |
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379 | quotient. |
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380 | |
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381 | `(smin:M X Y)' |
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382 | `(smax:M X Y)' |
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383 | Represents the smaller (for `smin') or larger (for `smax') of X |
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384 | and Y, interpreted as signed integers in mode M. |
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385 | |
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386 | `(umin:M X Y)' |
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387 | `(umax:M X Y)' |
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388 | Like `smin' and `smax', but the values are interpreted as unsigned |
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389 | integers. |
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390 | |
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391 | `(not:M X)' |
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392 | Represents the bitwise complement of the value represented by X, |
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393 | carried out in mode M, which must be a fixed-point machine mode. |
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394 | |
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395 | `(and:M X Y)' |
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396 | Represents the bitwise logical-and of the values represented by X |
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397 | and Y, carried out in machine mode M, which must be a fixed-point |
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398 | machine mode. |
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399 | |
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400 | `(ior:M X Y)' |
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401 | Represents the bitwise inclusive-or of the values represented by X |
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402 | and Y, carried out in machine mode M, which must be a fixed-point |
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403 | mode. |
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404 | |
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405 | `(xor:M X Y)' |
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406 | Represents the bitwise exclusive-or of the values represented by X |
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407 | and Y, carried out in machine mode M, which must be a fixed-point |
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408 | mode. |
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409 | |
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410 | `(ashift:M X C)' |
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411 | Represents the result of arithmetically shifting X left by C |
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412 | places. X have mode M, a fixed-point machine mode. C be a |
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413 | fixed-point mode or be a constant with mode `VOIDmode'; which mode |
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414 | is determined by the mode called for in the machine description |
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415 | entry for the left-shift instruction. For example, on the Vax, |
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416 | the mode of C is `QImode' regardless of M. |
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417 | |
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418 | `(lshiftrt:M X C)' |
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419 | `(ashiftrt:M X C)' |
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420 | Like `ashift' but for right shift. Unlike the case for left shift, |
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421 | these two operations are distinct. |
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422 | |
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423 | `(rotate:M X C)' |
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424 | `(rotatert:M X C)' |
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425 | Similar but represent left and right rotate. If C is a constant, |
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426 | use `rotate'. |
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427 | |
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428 | `(abs:M X)' |
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429 | Represents the absolute value of X, computed in mode M. |
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430 | |
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431 | `(sqrt:M X)' |
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432 | Represents the square root of X, computed in mode M. Most often M |
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433 | will be a floating point mode. |
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434 | |
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435 | `(ffs:M X)' |
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436 | Represents one plus the index of the least significant 1-bit in X, |
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437 | represented as an integer of mode M. (The value is zero if X is |
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438 | zero.) The mode of X need not be M; depending on the target |
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439 | machine, various mode combinations may be valid. |
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440 | |
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441 | |
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442 | File: gcc.info, Node: Comparisons, Next: Bit Fields, Prev: Arithmetic, Up: RTL |
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443 | |
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444 | Comparison Operations |
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445 | ===================== |
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446 | |
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447 | Comparison operators test a relation on two operands and are |
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448 | considered to represent a machine-dependent nonzero value described by, |
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449 | but not necessarily equal to, `STORE_FLAG_VALUE' (*note Misc::.) if the |
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450 | relation holds, or zero if it does not. The mode of the comparison |
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451 | operation is independent of the mode of the data being compared. If |
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452 | the comparison operation is being tested (e.g., the first operand of an |
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453 | `if_then_else'), the mode must be `VOIDmode'. If the comparison |
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454 | operation is producing data to be stored in some variable, the mode |
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455 | must be in class `MODE_INT'. All comparison operations producing data |
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456 | must use the same mode, which is machine-specific. |
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457 | |
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458 | There are two ways that comparison operations may be used. The |
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459 | comparison operators may be used to compare the condition codes `(cc0)' |
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460 | against zero, as in `(eq (cc0) (const_int 0))'. Such a construct |
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461 | actually refers to the result of the preceding instruction in which the |
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462 | condition codes were set. The instructing setting the condition code |
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463 | must be adjacent to the instruction using the condition code; only |
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464 | `note' insns may separate them. |
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465 | |
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466 | Alternatively, a comparison operation may directly compare two data |
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467 | objects. The mode of the comparison is determined by the operands; they |
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468 | must both be valid for a common machine mode. A comparison with both |
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469 | operands constant would be invalid as the machine mode could not be |
---|
470 | deduced from it, but such a comparison should never exist in RTL due to |
---|
471 | constant folding. |
---|
472 | |
---|
473 | In the example above, if `(cc0)' were last set to `(compare X Y)', |
---|
474 | the comparison operation is identical to `(eq X Y)'. Usually only one |
---|
475 | style of comparisons is supported on a particular machine, but the |
---|
476 | combine pass will try to merge the operations to produce the `eq' shown |
---|
477 | in case it exists in the context of the particular insn involved. |
---|
478 | |
---|
479 | Inequality comparisons come in two flavors, signed and unsigned. |
---|
480 | Thus, there are distinct expression codes `gt' and `gtu' for signed and |
---|
481 | unsigned greater-than. These can produce different results for the same |
---|
482 | pair of integer values: for example, 1 is signed greater-than -1 but not |
---|
483 | unsigned greater-than, because -1 when regarded as unsigned is actually |
---|
484 | `0xffffffff' which is greater than 1. |
---|
485 | |
---|
486 | The signed comparisons are also used for floating point values. |
---|
487 | Floating point comparisons are distinguished by the machine modes of |
---|
488 | the operands. |
---|
489 | |
---|
490 | `(eq:M X Y)' |
---|
491 | 1 if the values represented by X and Y are equal, otherwise 0. |
---|
492 | |
---|
493 | `(ne:M X Y)' |
---|
494 | 1 if the values represented by X and Y are not equal, otherwise 0. |
---|
495 | |
---|
496 | `(gt:M X Y)' |
---|
497 | 1 if the X is greater than Y. If they are fixed-point, the |
---|
498 | comparison is done in a signed sense. |
---|
499 | |
---|
500 | `(gtu:M X Y)' |
---|
501 | Like `gt' but does unsigned comparison, on fixed-point numbers |
---|
502 | only. |
---|
503 | |
---|
504 | `(lt:M X Y)' |
---|
505 | `(ltu:M X Y)' |
---|
506 | Like `gt' and `gtu' but test for "less than". |
---|
507 | |
---|
508 | `(ge:M X Y)' |
---|
509 | `(geu:M X Y)' |
---|
510 | Like `gt' and `gtu' but test for "greater than or equal". |
---|
511 | |
---|
512 | `(le:M X Y)' |
---|
513 | `(leu:M X Y)' |
---|
514 | Like `gt' and `gtu' but test for "less than or equal". |
---|
515 | |
---|
516 | `(if_then_else COND THEN ELSE)' |
---|
517 | This is not a comparison operation but is listed here because it is |
---|
518 | always used in conjunction with a comparison operation. To be |
---|
519 | precise, COND is a comparison expression. This expression |
---|
520 | represents a choice, according to COND, between the value |
---|
521 | represented by THEN and the one represented by ELSE. |
---|
522 | |
---|
523 | On most machines, `if_then_else' expressions are valid only to |
---|
524 | express conditional jumps. |
---|
525 | |
---|
526 | `(cond [TEST1 VALUE1 TEST2 VALUE2 ...] DEFAULT)' |
---|
527 | Similar to `if_then_else', but more general. Each of TEST1, |
---|
528 | TEST2, ... is performed in turn. The result of this expression is |
---|
529 | the VALUE corresponding to the first non-zero test, or DEFAULT if |
---|
530 | none of the tests are non-zero expressions. |
---|
531 | |
---|
532 | This is currently not valid for instruction patterns and is |
---|
533 | supported only for insn attributes. *Note Insn Attributes::. |
---|
534 | |
---|
535 | |
---|
536 | File: gcc.info, Node: Bit Fields, Next: Conversions, Prev: Comparisons, Up: RTL |
---|
537 | |
---|
538 | Bit Fields |
---|
539 | ========== |
---|
540 | |
---|
541 | Special expression codes exist to represent bitfield instructions. |
---|
542 | These types of expressions are lvalues in RTL; they may appear on the |
---|
543 | left side of an assignment, indicating insertion of a value into the |
---|
544 | specified bit field. |
---|
545 | |
---|
546 | `(sign_extract:M LOC SIZE POS)' |
---|
547 | This represents a reference to a sign-extended bit field contained |
---|
548 | or starting in LOC (a memory or register reference). The bit field |
---|
549 | is SIZE bits wide and starts at bit POS. The compilation option |
---|
550 | `BITS_BIG_ENDIAN' says which end of the memory unit POS counts |
---|
551 | from. |
---|
552 | |
---|
553 | If LOC is in memory, its mode must be a single-byte integer mode. |
---|
554 | If LOC is in a register, the mode to use is specified by the |
---|
555 | operand of the `insv' or `extv' pattern (*note Standard Names::.) |
---|
556 | and is usually a full-word integer mode, which is the default if |
---|
557 | none is specified. |
---|
558 | |
---|
559 | The mode of POS is machine-specific and is also specified in the |
---|
560 | `insv' or `extv' pattern. |
---|
561 | |
---|
562 | The mode M is the same as the mode that would be used for LOC if |
---|
563 | it were a register. |
---|
564 | |
---|
565 | `(zero_extract:M LOC SIZE POS)' |
---|
566 | Like `sign_extract' but refers to an unsigned or zero-extended bit |
---|
567 | field. The same sequence of bits are extracted, but they are |
---|
568 | filled to an entire word with zeros instead of by sign-extension. |
---|
569 | |
---|
570 | |
---|
571 | File: gcc.info, Node: Conversions, Next: RTL Declarations, Prev: Bit Fields, Up: RTL |
---|
572 | |
---|
573 | Conversions |
---|
574 | =========== |
---|
575 | |
---|
576 | All conversions between machine modes must be represented by |
---|
577 | explicit conversion operations. For example, an expression which is |
---|
578 | the sum of a byte and a full word cannot be written as `(plus:SI |
---|
579 | (reg:QI 34) (reg:SI 80))' because the `plus' operation requires two |
---|
580 | operands of the same machine mode. Therefore, the byte-sized operand |
---|
581 | is enclosed in a conversion operation, as in |
---|
582 | |
---|
583 | (plus:SI (sign_extend:SI (reg:QI 34)) (reg:SI 80)) |
---|
584 | |
---|
585 | The conversion operation is not a mere placeholder, because there |
---|
586 | may be more than one way of converting from a given starting mode to |
---|
587 | the desired final mode. The conversion operation code says how to do |
---|
588 | it. |
---|
589 | |
---|
590 | For all conversion operations, X must not be `VOIDmode' because the |
---|
591 | mode in which to do the conversion would not be known. The conversion |
---|
592 | must either be done at compile-time or X must be placed into a register. |
---|
593 | |
---|
594 | `(sign_extend:M X)' |
---|
595 | Represents the result of sign-extending the value X to machine |
---|
596 | mode M. M must be a fixed-point mode and X a fixed-point value of |
---|
597 | a mode narrower than M. |
---|
598 | |
---|
599 | `(zero_extend:M X)' |
---|
600 | Represents the result of zero-extending the value X to machine |
---|
601 | mode M. M must be a fixed-point mode and X a fixed-point value of |
---|
602 | a mode narrower than M. |
---|
603 | |
---|
604 | `(float_extend:M X)' |
---|
605 | Represents the result of extending the value X to machine mode M. |
---|
606 | M must be a floating point mode and X a floating point value of a |
---|
607 | mode narrower than M. |
---|
608 | |
---|
609 | `(truncate:M X)' |
---|
610 | Represents the result of truncating the value X to machine mode M. |
---|
611 | M must be a fixed-point mode and X a fixed-point value of a mode |
---|
612 | wider than M. |
---|
613 | |
---|
614 | `(float_truncate:M X)' |
---|
615 | Represents the result of truncating the value X to machine mode M. |
---|
616 | M must be a floating point mode and X a floating point value of a |
---|
617 | mode wider than M. |
---|
618 | |
---|
619 | `(float:M X)' |
---|
620 | Represents the result of converting fixed point value X, regarded |
---|
621 | as signed, to floating point mode M. |
---|
622 | |
---|
623 | `(unsigned_float:M X)' |
---|
624 | Represents the result of converting fixed point value X, regarded |
---|
625 | as unsigned, to floating point mode M. |
---|
626 | |
---|
627 | `(fix:M X)' |
---|
628 | When M is a fixed point mode, represents the result of converting |
---|
629 | floating point value X to mode M, regarded as signed. How |
---|
630 | rounding is done is not specified, so this operation may be used |
---|
631 | validly in compiling C code only for integer-valued operands. |
---|
632 | |
---|
633 | `(unsigned_fix:M X)' |
---|
634 | Represents the result of converting floating point value X to |
---|
635 | fixed point mode M, regarded as unsigned. How rounding is done is |
---|
636 | not specified. |
---|
637 | |
---|
638 | `(fix:M X)' |
---|
639 | When M is a floating point mode, represents the result of |
---|
640 | converting floating point value X (valid for mode M) to an |
---|
641 | integer, still represented in floating point mode M, by rounding |
---|
642 | towards zero. |
---|
643 | |
---|
644 | |
---|
645 | File: gcc.info, Node: RTL Declarations, Next: Side Effects, Prev: Conversions, Up: RTL |
---|
646 | |
---|
647 | Declarations |
---|
648 | ============ |
---|
649 | |
---|
650 | Declaration expression codes do not represent arithmetic operations |
---|
651 | but rather state assertions about their operands. |
---|
652 | |
---|
653 | `(strict_low_part (subreg:M (reg:N R) 0))' |
---|
654 | This expression code is used in only one context: as the |
---|
655 | destination operand of a `set' expression. In addition, the |
---|
656 | operand of this expression must be a non-paradoxical `subreg' |
---|
657 | expression. |
---|
658 | |
---|
659 | The presence of `strict_low_part' says that the part of the |
---|
660 | register which is meaningful in mode N, but is not part of mode M, |
---|
661 | is not to be altered. Normally, an assignment to such a subreg is |
---|
662 | allowed to have undefined effects on the rest of the register when |
---|
663 | M is less than a word. |
---|
664 | |
---|
665 | |
---|
666 | File: gcc.info, Node: Side Effects, Next: Incdec, Prev: RTL Declarations, Up: RTL |
---|
667 | |
---|
668 | Side Effect Expressions |
---|
669 | ======================= |
---|
670 | |
---|
671 | The expression codes described so far represent values, not actions. |
---|
672 | But machine instructions never produce values; they are meaningful only |
---|
673 | for their side effects on the state of the machine. Special expression |
---|
674 | codes are used to represent side effects. |
---|
675 | |
---|
676 | The body of an instruction is always one of these side effect codes; |
---|
677 | the codes described above, which represent values, appear only as the |
---|
678 | operands of these. |
---|
679 | |
---|
680 | `(set LVAL X)' |
---|
681 | Represents the action of storing the value of X into the place |
---|
682 | represented by LVAL. LVAL must be an expression representing a |
---|
683 | place that can be stored in: `reg' (or `subreg' or |
---|
684 | `strict_low_part'), `mem', `pc' or `cc0'. |
---|
685 | |
---|
686 | If LVAL is a `reg', `subreg' or `mem', it has a machine mode; then |
---|
687 | X must be valid for that mode. |
---|
688 | |
---|
689 | If LVAL is a `reg' whose machine mode is less than the full width |
---|
690 | of the register, then it means that the part of the register |
---|
691 | specified by the machine mode is given the specified value and the |
---|
692 | rest of the register receives an undefined value. Likewise, if |
---|
693 | LVAL is a `subreg' whose machine mode is narrower than the mode of |
---|
694 | the register, the rest of the register can be changed in an |
---|
695 | undefined way. |
---|
696 | |
---|
697 | If LVAL is a `strict_low_part' of a `subreg', then the part of the |
---|
698 | register specified by the machine mode of the `subreg' is given |
---|
699 | the value X and the rest of the register is not changed. |
---|
700 | |
---|
701 | If LVAL is `(cc0)', it has no machine mode, and X may be either a |
---|
702 | `compare' expression or a value that may have any mode. The |
---|
703 | latter case represents a "test" instruction. The expression `(set |
---|
704 | (cc0) (reg:M N))' is equivalent to `(set (cc0) (compare (reg:M N) |
---|
705 | (const_int 0)))'. Use the former expression to save space during |
---|
706 | the compilation. |
---|
707 | |
---|
708 | If LVAL is `(pc)', we have a jump instruction, and the |
---|
709 | possibilities for X are very limited. It may be a `label_ref' |
---|
710 | expression (unconditional jump). It may be an `if_then_else' |
---|
711 | (conditional jump), in which case either the second or the third |
---|
712 | operand must be `(pc)' (for the case which does not jump) and the |
---|
713 | other of the two must be a `label_ref' (for the case which does |
---|
714 | jump). X may also be a `mem' or `(plus:SI (pc) Y)', where Y may |
---|
715 | be a `reg' or a `mem'; these unusual patterns are used to |
---|
716 | represent jumps through branch tables. |
---|
717 | |
---|
718 | If LVAL is neither `(cc0)' nor `(pc)', the mode of LVAL must not |
---|
719 | be `VOIDmode' and the mode of X must be valid for the mode of LVAL. |
---|
720 | |
---|
721 | LVAL is customarily accessed with the `SET_DEST' macro and X with |
---|
722 | the `SET_SRC' macro. |
---|
723 | |
---|
724 | `(return)' |
---|
725 | As the sole expression in a pattern, represents a return from the |
---|
726 | current function, on machines where this can be done with one |
---|
727 | instruction, such as Vaxes. On machines where a multi-instruction |
---|
728 | "epilogue" must be executed in order to return from the function, |
---|
729 | returning is done by jumping to a label which precedes the |
---|
730 | epilogue, and the `return' expression code is never used. |
---|
731 | |
---|
732 | Inside an `if_then_else' expression, represents the value to be |
---|
733 | placed in `pc' to return to the caller. |
---|
734 | |
---|
735 | Note that an insn pattern of `(return)' is logically equivalent to |
---|
736 | `(set (pc) (return))', but the latter form is never used. |
---|
737 | |
---|
738 | `(call FUNCTION NARGS)' |
---|
739 | Represents a function call. FUNCTION is a `mem' expression whose |
---|
740 | address is the address of the function to be called. NARGS is an |
---|
741 | expression which can be used for two purposes: on some machines it |
---|
742 | represents the number of bytes of stack argument; on others, it |
---|
743 | represents the number of argument registers. |
---|
744 | |
---|
745 | Each machine has a standard machine mode which FUNCTION must have. |
---|
746 | The machine description defines macro `FUNCTION_MODE' to expand |
---|
747 | into the requisite mode name. The purpose of this mode is to |
---|
748 | specify what kind of addressing is allowed, on machines where the |
---|
749 | allowed kinds of addressing depend on the machine mode being |
---|
750 | addressed. |
---|
751 | |
---|
752 | `(clobber X)' |
---|
753 | Represents the storing or possible storing of an unpredictable, |
---|
754 | undescribed value into X, which must be a `reg', `scratch' or |
---|
755 | `mem' expression. |
---|
756 | |
---|
757 | One place this is used is in string instructions that store |
---|
758 | standard values into particular hard registers. It may not be |
---|
759 | worth the trouble to describe the values that are stored, but it |
---|
760 | is essential to inform the compiler that the registers will be |
---|
761 | altered, lest it attempt to keep data in them across the string |
---|
762 | instruction. |
---|
763 | |
---|
764 | If X is `(mem:BLK (const_int 0))', it means that all memory |
---|
765 | locations must be presumed clobbered. |
---|
766 | |
---|
767 | Note that the machine description classifies certain hard |
---|
768 | registers as "call-clobbered". All function call instructions are |
---|
769 | assumed by default to clobber these registers, so there is no need |
---|
770 | to use `clobber' expressions to indicate this fact. Also, each |
---|
771 | function call is assumed to have the potential to alter any memory |
---|
772 | location, unless the function is declared `const'. |
---|
773 | |
---|
774 | If the last group of expressions in a `parallel' are each a |
---|
775 | `clobber' expression whose arguments are `reg' or `match_scratch' |
---|
776 | (*note RTL Template::.) expressions, the combiner phase can add |
---|
777 | the appropriate `clobber' expressions to an insn it has |
---|
778 | constructed when doing so will cause a pattern to be matched. |
---|
779 | |
---|
780 | This feature can be used, for example, on a machine that whose |
---|
781 | multiply and add instructions don't use an MQ register but which |
---|
782 | has an add-accumulate instruction that does clobber the MQ |
---|
783 | register. Similarly, a combined instruction might require a |
---|
784 | temporary register while the constituent instructions might not. |
---|
785 | |
---|
786 | When a `clobber' expression for a register appears inside a |
---|
787 | `parallel' with other side effects, the register allocator |
---|
788 | guarantees that the register is unoccupied both before and after |
---|
789 | that insn. However, the reload phase may allocate a register used |
---|
790 | for one of the inputs unless the `&' constraint is specified for |
---|
791 | the selected alternative (*note Modifiers::.). You can clobber |
---|
792 | either a specific hard register, a pseudo register, or a `scratch' |
---|
793 | expression; in the latter two cases, GNU CC will allocate a hard |
---|
794 | register that is available there for use as a temporary. |
---|
795 | |
---|
796 | For instructions that require a temporary register, you should use |
---|
797 | `scratch' instead of a pseudo-register because this will allow the |
---|
798 | combiner phase to add the `clobber' when required. You do this by |
---|
799 | coding (`clobber' (`match_scratch' ...)). If you do clobber a |
---|
800 | pseudo register, use one which appears nowhere else--generate a |
---|
801 | new one each time. Otherwise, you may confuse CSE. |
---|
802 | |
---|
803 | There is one other known use for clobbering a pseudo register in a |
---|
804 | `parallel': when one of the input operands of the insn is also |
---|
805 | clobbered by the insn. In this case, using the same pseudo |
---|
806 | register in the clobber and elsewhere in the insn produces the |
---|
807 | expected results. |
---|
808 | |
---|
809 | `(use X)' |
---|
810 | Represents the use of the value of X. It indicates that the value |
---|
811 | in X at this point in the program is needed, even though it may |
---|
812 | not be apparent why this is so. Therefore, the compiler will not |
---|
813 | attempt to delete previous instructions whose only effect is to |
---|
814 | store a value in X. X must be a `reg' expression. |
---|
815 | |
---|
816 | During the delayed branch scheduling phase, X may be an insn. |
---|
817 | This indicates that X previously was located at this place in the |
---|
818 | code and its data dependencies need to be taken into account. |
---|
819 | These `use' insns will be deleted before the delayed branch |
---|
820 | scheduling phase exits. |
---|
821 | |
---|
822 | `(parallel [X0 X1 ...])' |
---|
823 | Represents several side effects performed in parallel. The square |
---|
824 | brackets stand for a vector; the operand of `parallel' is a vector |
---|
825 | of expressions. X0, X1 and so on are individual side effect |
---|
826 | expressions--expressions of code `set', `call', `return', |
---|
827 | `clobber' or `use'. |
---|
828 | |
---|
829 | "In parallel" means that first all the values used in the |
---|
830 | individual side-effects are computed, and second all the actual |
---|
831 | side-effects are performed. For example, |
---|
832 | |
---|
833 | (parallel [(set (reg:SI 1) (mem:SI (reg:SI 1))) |
---|
834 | (set (mem:SI (reg:SI 1)) (reg:SI 1))]) |
---|
835 | |
---|
836 | says unambiguously that the values of hard register 1 and the |
---|
837 | memory location addressed by it are interchanged. In both places |
---|
838 | where `(reg:SI 1)' appears as a memory address it refers to the |
---|
839 | value in register 1 *before* the execution of the insn. |
---|
840 | |
---|
841 | It follows that it is *incorrect* to use `parallel' and expect the |
---|
842 | result of one `set' to be available for the next one. For |
---|
843 | example, people sometimes attempt to represent a jump-if-zero |
---|
844 | instruction this way: |
---|
845 | |
---|
846 | (parallel [(set (cc0) (reg:SI 34)) |
---|
847 | (set (pc) (if_then_else |
---|
848 | (eq (cc0) (const_int 0)) |
---|
849 | (label_ref ...) |
---|
850 | (pc)))]) |
---|
851 | |
---|
852 | But this is incorrect, because it says that the jump condition |
---|
853 | depends on the condition code value *before* this instruction, not |
---|
854 | on the new value that is set by this instruction. |
---|
855 | |
---|
856 | Peephole optimization, which takes place together with final |
---|
857 | assembly code output, can produce insns whose patterns consist of |
---|
858 | a `parallel' whose elements are the operands needed to output the |
---|
859 | resulting assembler code--often `reg', `mem' or constant |
---|
860 | expressions. This would not be well-formed RTL at any other stage |
---|
861 | in compilation, but it is ok then because no further optimization |
---|
862 | remains to be done. However, the definition of the macro |
---|
863 | `NOTICE_UPDATE_CC', if any, must deal with such insns if you |
---|
864 | define any peephole optimizations. |
---|
865 | |
---|
866 | `(sequence [INSNS ...])' |
---|
867 | Represents a sequence of insns. Each of the INSNS that appears in |
---|
868 | the vector is suitable for appearing in the chain of insns, so it |
---|
869 | must be an `insn', `jump_insn', `call_insn', `code_label', |
---|
870 | `barrier' or `note'. |
---|
871 | |
---|
872 | A `sequence' RTX is never placed in an actual insn during RTL |
---|
873 | generation. It represents the sequence of insns that result from a |
---|
874 | `define_expand' *before* those insns are passed to `emit_insn' to |
---|
875 | insert them in the chain of insns. When actually inserted, the |
---|
876 | individual sub-insns are separated out and the `sequence' is |
---|
877 | forgotten. |
---|
878 | |
---|
879 | After delay-slot scheduling is completed, an insn and all the |
---|
880 | insns that reside in its delay slots are grouped together into a |
---|
881 | `sequence'. The insn requiring the delay slot is the first insn |
---|
882 | in the vector; subsequent insns are to be placed in the delay slot. |
---|
883 | |
---|
884 | `INSN_ANNULLED_BRANCH_P' is set on an insn in a delay slot to |
---|
885 | indicate that a branch insn should be used that will conditionally |
---|
886 | annul the effect of the insns in the delay slots. In such a case, |
---|
887 | `INSN_FROM_TARGET_P' indicates that the insn is from the target of |
---|
888 | the branch and should be executed only if the branch is taken; |
---|
889 | otherwise the insn should be executed only if the branch is not |
---|
890 | taken. *Note Delay Slots::. |
---|
891 | |
---|
892 | These expression codes appear in place of a side effect, as the body |
---|
893 | of an insn, though strictly speaking they do not always describe side |
---|
894 | effects as such: |
---|
895 | |
---|
896 | `(asm_input S)' |
---|
897 | Represents literal assembler code as described by the string S. |
---|
898 | |
---|
899 | `(unspec [OPERANDS ...] INDEX)' |
---|
900 | `(unspec_volatile [OPERANDS ...] INDEX)' |
---|
901 | Represents a machine-specific operation on OPERANDS. INDEX |
---|
902 | selects between multiple machine-specific operations. |
---|
903 | `unspec_volatile' is used for volatile operations and operations |
---|
904 | that may trap; `unspec' is used for other operations. |
---|
905 | |
---|
906 | These codes may appear inside a `pattern' of an insn, inside a |
---|
907 | `parallel', or inside an expression. |
---|
908 | |
---|
909 | `(addr_vec:M [LR0 LR1 ...])' |
---|
910 | Represents a table of jump addresses. The vector elements LR0, |
---|
911 | etc., are `label_ref' expressions. The mode M specifies how much |
---|
912 | space is given to each address; normally M would be `Pmode'. |
---|
913 | |
---|
914 | `(addr_diff_vec:M BASE [LR0 LR1 ...])' |
---|
915 | Represents a table of jump addresses expressed as offsets from |
---|
916 | BASE. The vector elements LR0, etc., are `label_ref' expressions |
---|
917 | and so is BASE. The mode M specifies how much space is given to |
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918 | each address-difference. |
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919 | |
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920 | |
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921 | File: gcc.info, Node: Incdec, Next: Assembler, Prev: Side Effects, Up: RTL |
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922 | |
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923 | Embedded Side-Effects on Addresses |
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924 | ================================== |
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925 | |
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926 | Four special side-effect expression codes appear as memory addresses. |
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927 | |
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928 | `(pre_dec:M X)' |
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929 | Represents the side effect of decrementing X by a standard amount |
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930 | and represents also the value that X has after being decremented. |
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931 | X must be a `reg' or `mem', but most machines allow only a `reg'. |
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932 | M must be the machine mode for pointers on the machine in use. |
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933 | The amount X is decremented by is the length in bytes of the |
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934 | machine mode of the containing memory reference of which this |
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935 | expression serves as the address. Here is an example of its use: |
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936 | |
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937 | (mem:DF (pre_dec:SI (reg:SI 39))) |
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938 | |
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939 | This says to decrement pseudo register 39 by the length of a |
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940 | `DFmode' value and use the result to address a `DFmode' value. |
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941 | |
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942 | `(pre_inc:M X)' |
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943 | Similar, but specifies incrementing X instead of decrementing it. |
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944 | |
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945 | `(post_dec:M X)' |
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946 | Represents the same side effect as `pre_dec' but a different |
---|
947 | value. The value represented here is the value X has before being |
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948 | decremented. |
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949 | |
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950 | `(post_inc:M X)' |
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951 | Similar, but specifies incrementing X instead of decrementing it. |
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952 | |
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953 | These embedded side effect expressions must be used with care. |
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954 | Instruction patterns may not use them. Until the `flow' pass of the |
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955 | compiler, they may occur only to represent pushes onto the stack. The |
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956 | `flow' pass finds cases where registers are incremented or decremented |
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957 | in one instruction and used as an address shortly before or after; |
---|
958 | these cases are then transformed to use pre- or post-increment or |
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959 | -decrement. |
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960 | |
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961 | If a register used as the operand of these expressions is used in |
---|
962 | another address in an insn, the original value of the register is used. |
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963 | Uses of the register outside of an address are not permitted within the |
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964 | same insn as a use in an embedded side effect expression because such |
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965 | insns behave differently on different machines and hence must be treated |
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966 | as ambiguous and disallowed. |
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967 | |
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968 | An instruction that can be represented with an embedded side effect |
---|
969 | could also be represented using `parallel' containing an additional |
---|
970 | `set' to describe how the address register is altered. This is not |
---|
971 | done because machines that allow these operations at all typically |
---|
972 | allow them wherever a memory address is called for. Describing them as |
---|
973 | additional parallel stores would require doubling the number of entries |
---|
974 | in the machine description. |
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975 | |
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976 | |
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977 | File: gcc.info, Node: Assembler, Next: Insns, Prev: Incdec, Up: RTL |
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978 | |
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979 | Assembler Instructions as Expressions |
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980 | ===================================== |
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981 | |
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982 | The RTX code `asm_operands' represents a value produced by a |
---|
983 | user-specified assembler instruction. It is used to represent an `asm' |
---|
984 | statement with arguments. An `asm' statement with a single output |
---|
985 | operand, like this: |
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986 | |
---|
987 | asm ("foo %1,%2,%0" : "=a" (outputvar) : "g" (x + y), "di" (*z)); |
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988 | |
---|
989 | is represented using a single `asm_operands' RTX which represents the |
---|
990 | value that is stored in `outputvar': |
---|
991 | |
---|
992 | (set RTX-FOR-OUTPUTVAR |
---|
993 | (asm_operands "foo %1,%2,%0" "a" 0 |
---|
994 | [RTX-FOR-ADDITION-RESULT RTX-FOR-*Z] |
---|
995 | [(asm_input:M1 "g") |
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996 | (asm_input:M2 "di")])) |
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997 | |
---|
998 | Here the operands of the `asm_operands' RTX are the assembler template |
---|
999 | string, the output-operand's constraint, the index-number of the output |
---|
1000 | operand among the output operands specified, a vector of input operand |
---|
1001 | RTX's, and a vector of input-operand modes and constraints. The mode |
---|
1002 | M1 is the mode of the sum `x+y'; M2 is that of `*z'. |
---|
1003 | |
---|
1004 | When an `asm' statement has multiple output values, its insn has |
---|
1005 | several such `set' RTX's inside of a `parallel'. Each `set' contains a |
---|
1006 | `asm_operands'; all of these share the same assembler template and |
---|
1007 | vectors, but each contains the constraint for the respective output |
---|
1008 | operand. They are also distinguished by the output-operand index |
---|
1009 | number, which is 0, 1, ... for successive output operands. |
---|
1010 | |
---|