1 | This is Info file gcc.info, produced by Makeinfo-1.55 from the input |
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2 | file gcc.texi. |
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3 | |
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4 | This file documents the use and the internals of the GNU compiler. |
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5 | |
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6 | Published by the Free Software Foundation 59 Temple Place - Suite 330 |
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7 | Boston, MA 02111-1307 USA |
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8 | |
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9 | Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995 Free Software |
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10 | Foundation, Inc. |
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11 | |
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12 | Permission is granted to make and distribute verbatim copies of this |
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13 | manual provided the copyright notice and this permission notice are |
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14 | preserved on all copies. |
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15 | |
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16 | Permission is granted to copy and distribute modified versions of |
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17 | this manual under the conditions for verbatim copying, provided also |
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18 | that the sections entitled "GNU General Public License," "Funding for |
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19 | Free Software," and "Protect Your Freedom--Fight `Look And Feel'" are |
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20 | included exactly as in the original, and provided that the entire |
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21 | resulting derived work is distributed under the terms of a permission |
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22 | notice identical to this one. |
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23 | |
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24 | Permission is granted to copy and distribute translations of this |
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25 | manual into another language, under the above conditions for modified |
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26 | versions, except that the sections entitled "GNU General Public |
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27 | License," "Funding for Free Software," and "Protect Your Freedom--Fight |
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28 | `Look And Feel'", and this permission notice, may be included in |
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29 | translations approved by the Free Software Foundation instead of in the |
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30 | original English. |
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31 | |
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32 | |
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33 | File: gcc.info, Node: Expander Definitions, Next: Insn Splitting, Prev: Peephole Definitions, Up: Machine Desc |
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34 | |
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35 | Defining RTL Sequences for Code Generation |
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36 | ========================================== |
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37 | |
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38 | On some target machines, some standard pattern names for RTL |
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39 | generation cannot be handled with single insn, but a sequence of RTL |
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40 | insns can represent them. For these target machines, you can write a |
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41 | `define_expand' to specify how to generate the sequence of RTL. |
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42 | |
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43 | A `define_expand' is an RTL expression that looks almost like a |
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44 | `define_insn'; but, unlike the latter, a `define_expand' is used only |
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45 | for RTL generation and it can produce more than one RTL insn. |
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46 | |
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47 | A `define_expand' RTX has four operands: |
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48 | |
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49 | * The name. Each `define_expand' must have a name, since the only |
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50 | use for it is to refer to it by name. |
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51 | |
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52 | * The RTL template. This is just like the RTL template for a |
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53 | `define_peephole' in that it is a vector of RTL expressions each |
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54 | being one insn. |
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55 | |
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56 | * The condition, a string containing a C expression. This |
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57 | expression is used to express how the availability of this pattern |
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58 | depends on subclasses of target machine, selected by command-line |
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59 | options when GNU CC is run. This is just like the condition of a |
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60 | `define_insn' that has a standard name. Therefore, the condition |
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61 | (if present) may not depend on the data in the insn being matched, |
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62 | but only the target-machine-type flags. The compiler needs to |
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63 | test these conditions during initialization in order to learn |
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64 | exactly which named instructions are available in a particular run. |
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65 | |
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66 | * The preparation statements, a string containing zero or more C |
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67 | statements which are to be executed before RTL code is generated |
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68 | from the RTL template. |
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69 | |
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70 | Usually these statements prepare temporary registers for use as |
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71 | internal operands in the RTL template, but they can also generate |
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72 | RTL insns directly by calling routines such as `emit_insn', etc. |
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73 | Any such insns precede the ones that come from the RTL template. |
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74 | |
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75 | Every RTL insn emitted by a `define_expand' must match some |
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76 | `define_insn' in the machine description. Otherwise, the compiler will |
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77 | crash when trying to generate code for the insn or trying to optimize |
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78 | it. |
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79 | |
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80 | The RTL template, in addition to controlling generation of RTL insns, |
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81 | also describes the operands that need to be specified when this pattern |
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82 | is used. In particular, it gives a predicate for each operand. |
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83 | |
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84 | A true operand, which needs to be specified in order to generate RTL |
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85 | from the pattern, should be described with a `match_operand' in its |
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86 | first occurrence in the RTL template. This enters information on the |
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87 | operand's predicate into the tables that record such things. GNU CC |
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88 | uses the information to preload the operand into a register if that is |
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89 | required for valid RTL code. If the operand is referred to more than |
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90 | once, subsequent references should use `match_dup'. |
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91 | |
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92 | The RTL template may also refer to internal "operands" which are |
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93 | temporary registers or labels used only within the sequence made by the |
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94 | `define_expand'. Internal operands are substituted into the RTL |
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95 | template with `match_dup', never with `match_operand'. The values of |
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96 | the internal operands are not passed in as arguments by the compiler |
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97 | when it requests use of this pattern. Instead, they are computed |
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98 | within the pattern, in the preparation statements. These statements |
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99 | compute the values and store them into the appropriate elements of |
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100 | `operands' so that `match_dup' can find them. |
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101 | |
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102 | There are two special macros defined for use in the preparation |
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103 | statements: `DONE' and `FAIL'. Use them with a following semicolon, as |
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104 | a statement. |
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105 | |
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106 | `DONE' |
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107 | Use the `DONE' macro to end RTL generation for the pattern. The |
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108 | only RTL insns resulting from the pattern on this occasion will be |
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109 | those already emitted by explicit calls to `emit_insn' within the |
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110 | preparation statements; the RTL template will not be generated. |
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111 | |
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112 | `FAIL' |
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113 | Make the pattern fail on this occasion. When a pattern fails, it |
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114 | means that the pattern was not truly available. The calling |
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115 | routines in the compiler will try other strategies for code |
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116 | generation using other patterns. |
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117 | |
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118 | Failure is currently supported only for binary (addition, |
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119 | multiplication, shifting, etc.) and bitfield (`extv', `extzv', and |
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120 | `insv') operations. |
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121 | |
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122 | Here is an example, the definition of left-shift for the SPUR chip: |
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123 | |
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124 | (define_expand "ashlsi3" |
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125 | [(set (match_operand:SI 0 "register_operand" "") |
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126 | (ashift:SI |
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127 | |
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128 | (match_operand:SI 1 "register_operand" "") |
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129 | (match_operand:SI 2 "nonmemory_operand" "")))] |
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130 | "" |
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131 | " |
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132 | |
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133 | { |
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134 | if (GET_CODE (operands[2]) != CONST_INT |
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135 | || (unsigned) INTVAL (operands[2]) > 3) |
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136 | FAIL; |
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137 | }") |
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138 | |
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139 | This example uses `define_expand' so that it can generate an RTL insn |
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140 | for shifting when the shift-count is in the supported range of 0 to 3 |
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141 | but fail in other cases where machine insns aren't available. When it |
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142 | fails, the compiler tries another strategy using different patterns |
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143 | (such as, a library call). |
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144 | |
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145 | If the compiler were able to handle nontrivial condition-strings in |
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146 | patterns with names, then it would be possible to use a `define_insn' |
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147 | in that case. Here is another case (zero-extension on the 68000) which |
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148 | makes more use of the power of `define_expand': |
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149 | |
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150 | (define_expand "zero_extendhisi2" |
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151 | [(set (match_operand:SI 0 "general_operand" "") |
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152 | (const_int 0)) |
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153 | (set (strict_low_part |
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154 | (subreg:HI |
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155 | (match_dup 0) |
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156 | 0)) |
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157 | (match_operand:HI 1 "general_operand" ""))] |
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158 | "" |
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159 | "operands[1] = make_safe_from (operands[1], operands[0]);") |
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160 | |
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161 | Here two RTL insns are generated, one to clear the entire output operand |
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162 | and the other to copy the input operand into its low half. This |
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163 | sequence is incorrect if the input operand refers to [the old value of] |
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164 | the output operand, so the preparation statement makes sure this isn't |
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165 | so. The function `make_safe_from' copies the `operands[1]' into a |
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166 | temporary register if it refers to `operands[0]'. It does this by |
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167 | emitting another RTL insn. |
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168 | |
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169 | Finally, a third example shows the use of an internal operand. |
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170 | Zero-extension on the SPUR chip is done by `and'-ing the result against |
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171 | a halfword mask. But this mask cannot be represented by a `const_int' |
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172 | because the constant value is too large to be legitimate on this |
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173 | machine. So it must be copied into a register with `force_reg' and |
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174 | then the register used in the `and'. |
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175 | |
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176 | (define_expand "zero_extendhisi2" |
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177 | [(set (match_operand:SI 0 "register_operand" "") |
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178 | (and:SI (subreg:SI |
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179 | (match_operand:HI 1 "register_operand" "") |
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180 | 0) |
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181 | (match_dup 2)))] |
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182 | "" |
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183 | "operands[2] |
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184 | = force_reg (SImode, gen_rtx (CONST_INT, |
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185 | VOIDmode, 65535)); ") |
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186 | |
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187 | *Note:* If the `define_expand' is used to serve a standard binary or |
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188 | unary arithmetic operation or a bitfield operation, then the last insn |
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189 | it generates must not be a `code_label', `barrier' or `note'. It must |
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190 | be an `insn', `jump_insn' or `call_insn'. If you don't need a real insn |
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191 | at the end, emit an insn to copy the result of the operation into |
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192 | itself. Such an insn will generate no code, but it can avoid problems |
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193 | in the compiler. |
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194 | |
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195 | |
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196 | File: gcc.info, Node: Insn Splitting, Next: Insn Attributes, Prev: Expander Definitions, Up: Machine Desc |
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197 | |
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198 | Defining How to Split Instructions |
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199 | ================================== |
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200 | |
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201 | There are two cases where you should specify how to split a pattern |
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202 | into multiple insns. On machines that have instructions requiring delay |
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203 | slots (*note Delay Slots::.) or that have instructions whose output is |
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204 | not available for multiple cycles (*note Function Units::.), the |
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205 | compiler phases that optimize these cases need to be able to move insns |
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206 | into one-instruction delay slots. However, some insns may generate |
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207 | more than one machine instruction. These insns cannot be placed into a |
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208 | delay slot. |
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209 | |
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210 | Often you can rewrite the single insn as a list of individual insns, |
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211 | each corresponding to one machine instruction. The disadvantage of |
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212 | doing so is that it will cause the compilation to be slower and require |
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213 | more space. If the resulting insns are too complex, it may also |
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214 | suppress some optimizations. The compiler splits the insn if there is a |
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215 | reason to believe that it might improve instruction or delay slot |
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216 | scheduling. |
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217 | |
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218 | The insn combiner phase also splits putative insns. If three insns |
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219 | are merged into one insn with a complex expression that cannot be |
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220 | matched by some `define_insn' pattern, the combiner phase attempts to |
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221 | split the complex pattern into two insns that are recognized. Usually |
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222 | it can break the complex pattern into two patterns by splitting out some |
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223 | subexpression. However, in some other cases, such as performing an |
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224 | addition of a large constant in two insns on a RISC machine, the way to |
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225 | split the addition into two insns is machine-dependent. |
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226 | |
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227 | The `define_split' definition tells the compiler how to split a |
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228 | complex insn into several simpler insns. It looks like this: |
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229 | |
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230 | (define_split |
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231 | [INSN-PATTERN] |
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232 | "CONDITION" |
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233 | [NEW-INSN-PATTERN-1 |
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234 | NEW-INSN-PATTERN-2 |
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235 | ...] |
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236 | "PREPARATION STATEMENTS") |
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237 | |
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238 | INSN-PATTERN is a pattern that needs to be split and CONDITION is |
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239 | the final condition to be tested, as in a `define_insn'. When an insn |
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240 | matching INSN-PATTERN and satisfying CONDITION is found, it is replaced |
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241 | in the insn list with the insns given by NEW-INSN-PATTERN-1, |
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242 | NEW-INSN-PATTERN-2, etc. |
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243 | |
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244 | The PREPARATION STATEMENTS are similar to those statements that are |
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245 | specified for `define_expand' (*note Expander Definitions::.) and are |
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246 | executed before the new RTL is generated to prepare for the generated |
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247 | code or emit some insns whose pattern is not fixed. Unlike those in |
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248 | `define_expand', however, these statements must not generate any new |
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249 | pseudo-registers. Once reload has completed, they also must not |
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250 | allocate any space in the stack frame. |
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251 | |
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252 | Patterns are matched against INSN-PATTERN in two different |
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253 | circumstances. If an insn needs to be split for delay slot scheduling |
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254 | or insn scheduling, the insn is already known to be valid, which means |
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255 | that it must have been matched by some `define_insn' and, if |
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256 | `reload_completed' is non-zero, is known to satisfy the constraints of |
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257 | that `define_insn'. In that case, the new insn patterns must also be |
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258 | insns that are matched by some `define_insn' and, if `reload_completed' |
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259 | is non-zero, must also satisfy the constraints of those definitions. |
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260 | |
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261 | As an example of this usage of `define_split', consider the following |
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262 | example from `a29k.md', which splits a `sign_extend' from `HImode' to |
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263 | `SImode' into a pair of shift insns: |
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264 | |
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265 | (define_split |
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266 | [(set (match_operand:SI 0 "gen_reg_operand" "") |
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267 | (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))] |
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268 | "" |
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269 | [(set (match_dup 0) |
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270 | (ashift:SI (match_dup 1) |
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271 | (const_int 16))) |
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272 | (set (match_dup 0) |
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273 | (ashiftrt:SI (match_dup 0) |
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274 | (const_int 16)))] |
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275 | " |
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276 | { operands[1] = gen_lowpart (SImode, operands[1]); }") |
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277 | |
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278 | When the combiner phase tries to split an insn pattern, it is always |
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279 | the case that the pattern is *not* matched by any `define_insn'. The |
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280 | combiner pass first tries to split a single `set' expression and then |
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281 | the same `set' expression inside a `parallel', but followed by a |
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282 | `clobber' of a pseudo-reg to use as a scratch register. In these |
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283 | cases, the combiner expects exactly two new insn patterns to be |
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284 | generated. It will verify that these patterns match some `define_insn' |
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285 | definitions, so you need not do this test in the `define_split' (of |
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286 | course, there is no point in writing a `define_split' that will never |
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287 | produce insns that match). |
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288 | |
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289 | Here is an example of this use of `define_split', taken from |
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290 | `rs6000.md': |
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291 | |
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292 | (define_split |
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293 | [(set (match_operand:SI 0 "gen_reg_operand" "") |
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294 | (plus:SI (match_operand:SI 1 "gen_reg_operand" "") |
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295 | (match_operand:SI 2 "non_add_cint_operand" "")))] |
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296 | "" |
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297 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) |
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298 | (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] |
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299 | " |
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300 | { |
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301 | int low = INTVAL (operands[2]) & 0xffff; |
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302 | int high = (unsigned) INTVAL (operands[2]) >> 16; |
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303 | |
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304 | if (low & 0x8000) |
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305 | high++, low |= 0xffff0000; |
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306 | |
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307 | operands[3] = gen_rtx (CONST_INT, VOIDmode, high << 16); |
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308 | operands[4] = gen_rtx (CONST_INT, VOIDmode, low); |
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309 | }") |
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310 | |
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311 | Here the predicate `non_add_cint_operand' matches any `const_int' |
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312 | that is *not* a valid operand of a single add insn. The add with the |
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313 | smaller displacement is written so that it can be substituted into the |
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314 | address of a subsequent operation. |
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315 | |
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316 | An example that uses a scratch register, from the same file, |
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317 | generates an equality comparison of a register and a large constant: |
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318 | |
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319 | (define_split |
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320 | [(set (match_operand:CC 0 "cc_reg_operand" "") |
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321 | (compare:CC (match_operand:SI 1 "gen_reg_operand" "") |
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322 | (match_operand:SI 2 "non_short_cint_operand" ""))) |
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323 | (clobber (match_operand:SI 3 "gen_reg_operand" ""))] |
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324 | "find_single_use (operands[0], insn, 0) |
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325 | && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ |
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326 | || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" |
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327 | [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) |
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328 | (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] |
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329 | " |
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330 | { |
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331 | /* Get the constant we are comparing against, C, and see what it |
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332 | looks like sign-extended to 16 bits. Then see what constant |
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333 | could be XOR'ed with C to get the sign-extended value. */ |
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334 | |
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335 | int c = INTVAL (operands[2]); |
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336 | int sextc = (c << 16) >> 16; |
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337 | int xorv = c ^ sextc; |
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338 | |
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339 | operands[4] = gen_rtx (CONST_INT, VOIDmode, xorv); |
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340 | operands[5] = gen_rtx (CONST_INT, VOIDmode, sextc); |
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341 | }") |
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342 | |
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343 | To avoid confusion, don't write a single `define_split' that accepts |
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344 | some insns that match some `define_insn' as well as some insns that |
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345 | don't. Instead, write two separate `define_split' definitions, one for |
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346 | the insns that are valid and one for the insns that are not valid. |
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347 | |
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348 | |
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349 | File: gcc.info, Node: Insn Attributes, Prev: Insn Splitting, Up: Machine Desc |
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350 | |
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351 | Instruction Attributes |
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352 | ====================== |
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353 | |
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354 | In addition to describing the instruction supported by the target |
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355 | machine, the `md' file also defines a group of "attributes" and a set of |
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356 | values for each. Every generated insn is assigned a value for each |
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357 | attribute. One possible attribute would be the effect that the insn |
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358 | has on the machine's condition code. This attribute can then be used |
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359 | by `NOTICE_UPDATE_CC' to track the condition codes. |
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360 | |
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361 | * Menu: |
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362 | |
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363 | * Defining Attributes:: Specifying attributes and their values. |
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364 | * Expressions:: Valid expressions for attribute values. |
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365 | * Tagging Insns:: Assigning attribute values to insns. |
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366 | * Attr Example:: An example of assigning attributes. |
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367 | * Insn Lengths:: Computing the length of insns. |
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368 | * Constant Attributes:: Defining attributes that are constant. |
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369 | * Delay Slots:: Defining delay slots required for a machine. |
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370 | * Function Units:: Specifying information for insn scheduling. |
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371 | |
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372 | |
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373 | File: gcc.info, Node: Defining Attributes, Next: Expressions, Up: Insn Attributes |
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374 | |
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375 | Defining Attributes and their Values |
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376 | ------------------------------------ |
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377 | |
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378 | The `define_attr' expression is used to define each attribute |
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379 | required by the target machine. It looks like: |
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380 | |
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381 | (define_attr NAME LIST-OF-VALUES DEFAULT) |
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382 | |
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383 | NAME is a string specifying the name of the attribute being defined. |
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384 | |
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385 | LIST-OF-VALUES is either a string that specifies a comma-separated |
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386 | list of values that can be assigned to the attribute, or a null string |
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387 | to indicate that the attribute takes numeric values. |
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388 | |
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389 | DEFAULT is an attribute expression that gives the value of this |
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390 | attribute for insns that match patterns whose definition does not |
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391 | include an explicit value for this attribute. *Note Attr Example::, |
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392 | for more information on the handling of defaults. *Note Constant |
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393 | Attributes::, for information on attributes that do not depend on any |
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394 | particular insn. |
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395 | |
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396 | For each defined attribute, a number of definitions are written to |
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397 | the `insn-attr.h' file. For cases where an explicit set of values is |
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398 | specified for an attribute, the following are defined: |
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399 | |
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400 | * A `#define' is written for the symbol `HAVE_ATTR_NAME'. |
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401 | |
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402 | * An enumeral class is defined for `attr_NAME' with elements of the |
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403 | form `UPPER-NAME_UPPER-VALUE' where the attribute name and value |
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404 | are first converted to upper case. |
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405 | |
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406 | * A function `get_attr_NAME' is defined that is passed an insn and |
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407 | returns the attribute value for that insn. |
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408 | |
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409 | For example, if the following is present in the `md' file: |
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410 | |
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411 | (define_attr "type" "branch,fp,load,store,arith" ...) |
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412 | |
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413 | the following lines will be written to the file `insn-attr.h'. |
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414 | |
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415 | #define HAVE_ATTR_type |
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416 | enum attr_type {TYPE_BRANCH, TYPE_FP, TYPE_LOAD, |
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417 | TYPE_STORE, TYPE_ARITH}; |
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418 | extern enum attr_type get_attr_type (); |
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419 | |
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420 | If the attribute takes numeric values, no `enum' type will be |
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421 | defined and the function to obtain the attribute's value will return |
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422 | `int'. |
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423 | |
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424 | |
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425 | File: gcc.info, Node: Expressions, Next: Tagging Insns, Prev: Defining Attributes, Up: Insn Attributes |
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426 | |
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427 | Attribute Expressions |
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428 | --------------------- |
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429 | |
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430 | RTL expressions used to define attributes use the codes described |
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431 | above plus a few specific to attribute definitions, to be discussed |
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432 | below. Attribute value expressions must have one of the following |
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433 | forms: |
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434 | |
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435 | `(const_int I)' |
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436 | The integer I specifies the value of a numeric attribute. I must |
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437 | be non-negative. |
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438 | |
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439 | The value of a numeric attribute can be specified either with a |
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440 | `const_int' or as an integer represented as a string in |
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441 | `const_string', `eq_attr' (see below), and `set_attr' (*note |
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442 | Tagging Insns::.) expressions. |
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443 | |
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444 | `(const_string VALUE)' |
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445 | The string VALUE specifies a constant attribute value. If VALUE |
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446 | is specified as `"*"', it means that the default value of the |
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447 | attribute is to be used for the insn containing this expression. |
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448 | `"*"' obviously cannot be used in the DEFAULT expression of a |
---|
449 | `define_attr'. |
---|
450 | |
---|
451 | If the attribute whose value is being specified is numeric, VALUE |
---|
452 | must be a string containing a non-negative integer (normally |
---|
453 | `const_int' would be used in this case). Otherwise, it must |
---|
454 | contain one of the valid values for the attribute. |
---|
455 | |
---|
456 | `(if_then_else TEST TRUE-VALUE FALSE-VALUE)' |
---|
457 | TEST specifies an attribute test, whose format is defined below. |
---|
458 | The value of this expression is TRUE-VALUE if TEST is true, |
---|
459 | otherwise it is FALSE-VALUE. |
---|
460 | |
---|
461 | `(cond [TEST1 VALUE1 ...] DEFAULT)' |
---|
462 | The first operand of this expression is a vector containing an even |
---|
463 | number of expressions and consisting of pairs of TEST and VALUE |
---|
464 | expressions. The value of the `cond' expression is that of the |
---|
465 | VALUE corresponding to the first true TEST expression. If none of |
---|
466 | the TEST expressions are true, the value of the `cond' expression |
---|
467 | is that of the DEFAULT expression. |
---|
468 | |
---|
469 | TEST expressions can have one of the following forms: |
---|
470 | |
---|
471 | `(const_int I)' |
---|
472 | This test is true if I is non-zero and false otherwise. |
---|
473 | |
---|
474 | `(not TEST)' |
---|
475 | `(ior TEST1 TEST2)' |
---|
476 | `(and TEST1 TEST2)' |
---|
477 | These tests are true if the indicated logical function is true. |
---|
478 | |
---|
479 | `(match_operand:M N PRED CONSTRAINTS)' |
---|
480 | This test is true if operand N of the insn whose attribute value |
---|
481 | is being determined has mode M (this part of the test is ignored |
---|
482 | if M is `VOIDmode') and the function specified by the string PRED |
---|
483 | returns a non-zero value when passed operand N and mode M (this |
---|
484 | part of the test is ignored if PRED is the null string). |
---|
485 | |
---|
486 | The CONSTRAINTS operand is ignored and should be the null string. |
---|
487 | |
---|
488 | `(le ARITH1 ARITH2)' |
---|
489 | `(leu ARITH1 ARITH2)' |
---|
490 | `(lt ARITH1 ARITH2)' |
---|
491 | `(ltu ARITH1 ARITH2)' |
---|
492 | `(gt ARITH1 ARITH2)' |
---|
493 | `(gtu ARITH1 ARITH2)' |
---|
494 | `(ge ARITH1 ARITH2)' |
---|
495 | `(geu ARITH1 ARITH2)' |
---|
496 | `(ne ARITH1 ARITH2)' |
---|
497 | `(eq ARITH1 ARITH2)' |
---|
498 | These tests are true if the indicated comparison of the two |
---|
499 | arithmetic expressions is true. Arithmetic expressions are formed |
---|
500 | with `plus', `minus', `mult', `div', `mod', `abs', `neg', `and', |
---|
501 | `ior', `xor', `not', `ashift', `lshiftrt', and `ashiftrt' |
---|
502 | expressions. |
---|
503 | |
---|
504 | `const_int' and `symbol_ref' are always valid terms (*note Insn |
---|
505 | Lengths::.,for additional forms). `symbol_ref' is a string |
---|
506 | denoting a C expression that yields an `int' when evaluated by the |
---|
507 | `get_attr_...' routine. It should normally be a global variable. |
---|
508 | |
---|
509 | `(eq_attr NAME VALUE)' |
---|
510 | NAME is a string specifying the name of an attribute. |
---|
511 | |
---|
512 | VALUE is a string that is either a valid value for attribute NAME, |
---|
513 | a comma-separated list of values, or `!' followed by a value or |
---|
514 | list. If VALUE does not begin with a `!', this test is true if |
---|
515 | the value of the NAME attribute of the current insn is in the list |
---|
516 | specified by VALUE. If VALUE begins with a `!', this test is true |
---|
517 | if the attribute's value is *not* in the specified list. |
---|
518 | |
---|
519 | For example, |
---|
520 | |
---|
521 | (eq_attr "type" "load,store") |
---|
522 | |
---|
523 | is equivalent to |
---|
524 | |
---|
525 | (ior (eq_attr "type" "load") (eq_attr "type" "store")) |
---|
526 | |
---|
527 | If NAME specifies an attribute of `alternative', it refers to the |
---|
528 | value of the compiler variable `which_alternative' (*note Output |
---|
529 | Statement::.) and the values must be small integers. For example, |
---|
530 | |
---|
531 | (eq_attr "alternative" "2,3") |
---|
532 | |
---|
533 | is equivalent to |
---|
534 | |
---|
535 | (ior (eq (symbol_ref "which_alternative") (const_int 2)) |
---|
536 | (eq (symbol_ref "which_alternative") (const_int 3))) |
---|
537 | |
---|
538 | Note that, for most attributes, an `eq_attr' test is simplified in |
---|
539 | cases where the value of the attribute being tested is known for |
---|
540 | all insns matching a particular pattern. This is by far the most |
---|
541 | common case. |
---|
542 | |
---|
543 | `(attr_flag NAME)' |
---|
544 | The value of an `attr_flag' expression is true if the flag |
---|
545 | specified by NAME is true for the `insn' currently being scheduled. |
---|
546 | |
---|
547 | NAME is a string specifying one of a fixed set of flags to test. |
---|
548 | Test the flags `forward' and `backward' to determine the direction |
---|
549 | of a conditional branch. Test the flags `very_likely', `likely', |
---|
550 | `very_unlikely', and `unlikely' to determine if a conditional |
---|
551 | branch is expected to be taken. |
---|
552 | |
---|
553 | If the `very_likely' flag is true, then the `likely' flag is also |
---|
554 | true. Likewise for the `very_unlikely' and `unlikely' flags. |
---|
555 | |
---|
556 | This example describes a conditional branch delay slot which can |
---|
557 | be nullified for forward branches that are taken (annul-true) or |
---|
558 | for backward branches which are not taken (annul-false). |
---|
559 | |
---|
560 | (define_delay (eq_attr "type" "cbranch") |
---|
561 | [(eq_attr "in_branch_delay" "true") |
---|
562 | (and (eq_attr "in_branch_delay" "true") |
---|
563 | (attr_flag "forward")) |
---|
564 | (and (eq_attr "in_branch_delay" "true") |
---|
565 | (attr_flag "backward"))]) |
---|
566 | |
---|
567 | The `forward' and `backward' flags are false if the current `insn' |
---|
568 | being scheduled is not a conditional branch. |
---|
569 | |
---|
570 | The `very_likely' and `likely' flags are true if the `insn' being |
---|
571 | scheduled is not a conditional branch. The The `very_unlikely' |
---|
572 | and `unlikely' flags are false if the `insn' being scheduled is |
---|
573 | not a conditional branch. |
---|
574 | |
---|
575 | `attr_flag' is only used during delay slot scheduling and has no |
---|
576 | meaning to other passes of the compiler. |
---|
577 | |
---|
578 | |
---|
579 | File: gcc.info, Node: Tagging Insns, Next: Attr Example, Prev: Expressions, Up: Insn Attributes |
---|
580 | |
---|
581 | Assigning Attribute Values to Insns |
---|
582 | ----------------------------------- |
---|
583 | |
---|
584 | The value assigned to an attribute of an insn is primarily |
---|
585 | determined by which pattern is matched by that insn (or which |
---|
586 | `define_peephole' generated it). Every `define_insn' and |
---|
587 | `define_peephole' can have an optional last argument to specify the |
---|
588 | values of attributes for matching insns. The value of any attribute |
---|
589 | not specified in a particular insn is set to the default value for that |
---|
590 | attribute, as specified in its `define_attr'. Extensive use of default |
---|
591 | values for attributes permits the specification of the values for only |
---|
592 | one or two attributes in the definition of most insn patterns, as seen |
---|
593 | in the example in the next section. |
---|
594 | |
---|
595 | The optional last argument of `define_insn' and `define_peephole' is |
---|
596 | a vector of expressions, each of which defines the value for a single |
---|
597 | attribute. The most general way of assigning an attribute's value is |
---|
598 | to use a `set' expression whose first operand is an `attr' expression |
---|
599 | giving the name of the attribute being set. The second operand of the |
---|
600 | `set' is an attribute expression (*note Expressions::.) giving the |
---|
601 | value of the attribute. |
---|
602 | |
---|
603 | When the attribute value depends on the `alternative' attribute |
---|
604 | (i.e., which is the applicable alternative in the constraint of the |
---|
605 | insn), the `set_attr_alternative' expression can be used. It allows |
---|
606 | the specification of a vector of attribute expressions, one for each |
---|
607 | alternative. |
---|
608 | |
---|
609 | When the generality of arbitrary attribute expressions is not |
---|
610 | required, the simpler `set_attr' expression can be used, which allows |
---|
611 | specifying a string giving either a single attribute value or a list of |
---|
612 | attribute values, one for each alternative. |
---|
613 | |
---|
614 | The form of each of the above specifications is shown below. In |
---|
615 | each case, NAME is a string specifying the attribute to be set. |
---|
616 | |
---|
617 | `(set_attr NAME VALUE-STRING)' |
---|
618 | VALUE-STRING is either a string giving the desired attribute value, |
---|
619 | or a string containing a comma-separated list giving the values for |
---|
620 | succeeding alternatives. The number of elements must match the |
---|
621 | number of alternatives in the constraint of the insn pattern. |
---|
622 | |
---|
623 | Note that it may be useful to specify `*' for some alternative, in |
---|
624 | which case the attribute will assume its default value for insns |
---|
625 | matching that alternative. |
---|
626 | |
---|
627 | `(set_attr_alternative NAME [VALUE1 VALUE2 ...])' |
---|
628 | Depending on the alternative of the insn, the value will be one of |
---|
629 | the specified values. This is a shorthand for using a `cond' with |
---|
630 | tests on the `alternative' attribute. |
---|
631 | |
---|
632 | `(set (attr NAME) VALUE)' |
---|
633 | The first operand of this `set' must be the special RTL expression |
---|
634 | `attr', whose sole operand is a string giving the name of the |
---|
635 | attribute being set. VALUE is the value of the attribute. |
---|
636 | |
---|
637 | The following shows three different ways of representing the same |
---|
638 | attribute value specification: |
---|
639 | |
---|
640 | (set_attr "type" "load,store,arith") |
---|
641 | |
---|
642 | (set_attr_alternative "type" |
---|
643 | [(const_string "load") (const_string "store") |
---|
644 | (const_string "arith")]) |
---|
645 | |
---|
646 | (set (attr "type") |
---|
647 | (cond [(eq_attr "alternative" "1") (const_string "load") |
---|
648 | (eq_attr "alternative" "2") (const_string "store")] |
---|
649 | (const_string "arith"))) |
---|
650 | |
---|
651 | The `define_asm_attributes' expression provides a mechanism to |
---|
652 | specify the attributes assigned to insns produced from an `asm' |
---|
653 | statement. It has the form: |
---|
654 | |
---|
655 | (define_asm_attributes [ATTR-SETS]) |
---|
656 | |
---|
657 | where ATTR-SETS is specified the same as for both the `define_insn' and |
---|
658 | the `define_peephole' expressions. |
---|
659 | |
---|
660 | These values will typically be the "worst case" attribute values. |
---|
661 | For example, they might indicate that the condition code will be |
---|
662 | clobbered. |
---|
663 | |
---|
664 | A specification for a `length' attribute is handled specially. The |
---|
665 | way to compute the length of an `asm' insn is to multiply the length |
---|
666 | specified in the expression `define_asm_attributes' by the number of |
---|
667 | machine instructions specified in the `asm' statement, determined by |
---|
668 | counting the number of semicolons and newlines in the string. |
---|
669 | Therefore, the value of the `length' attribute specified in a |
---|
670 | `define_asm_attributes' should be the maximum possible length of a |
---|
671 | single machine instruction. |
---|
672 | |
---|
673 | |
---|
674 | File: gcc.info, Node: Attr Example, Next: Insn Lengths, Prev: Tagging Insns, Up: Insn Attributes |
---|
675 | |
---|
676 | Example of Attribute Specifications |
---|
677 | ----------------------------------- |
---|
678 | |
---|
679 | The judicious use of defaulting is important in the efficient use of |
---|
680 | insn attributes. Typically, insns are divided into "types" and an |
---|
681 | attribute, customarily called `type', is used to represent this value. |
---|
682 | This attribute is normally used only to define the default value for |
---|
683 | other attributes. An example will clarify this usage. |
---|
684 | |
---|
685 | Assume we have a RISC machine with a condition code and in which only |
---|
686 | full-word operations are performed in registers. Let us assume that we |
---|
687 | can divide all insns into loads, stores, (integer) arithmetic |
---|
688 | operations, floating point operations, and branches. |
---|
689 | |
---|
690 | Here we will concern ourselves with determining the effect of an |
---|
691 | insn on the condition code and will limit ourselves to the following |
---|
692 | possible effects: The condition code can be set unpredictably |
---|
693 | (clobbered), not be changed, be set to agree with the results of the |
---|
694 | operation, or only changed if the item previously set into the |
---|
695 | condition code has been modified. |
---|
696 | |
---|
697 | Here is part of a sample `md' file for such a machine: |
---|
698 | |
---|
699 | (define_attr "type" "load,store,arith,fp,branch" (const_string "arith")) |
---|
700 | |
---|
701 | (define_attr "cc" "clobber,unchanged,set,change0" |
---|
702 | (cond [(eq_attr "type" "load") |
---|
703 | (const_string "change0") |
---|
704 | (eq_attr "type" "store,branch") |
---|
705 | (const_string "unchanged") |
---|
706 | (eq_attr "type" "arith") |
---|
707 | (if_then_else (match_operand:SI 0 "" "") |
---|
708 | (const_string "set") |
---|
709 | (const_string "clobber"))] |
---|
710 | (const_string "clobber"))) |
---|
711 | |
---|
712 | (define_insn "" |
---|
713 | [(set (match_operand:SI 0 "general_operand" "=r,r,m") |
---|
714 | (match_operand:SI 1 "general_operand" "r,m,r"))] |
---|
715 | "" |
---|
716 | "@ |
---|
717 | move %0,%1 |
---|
718 | load %0,%1 |
---|
719 | store %0,%1" |
---|
720 | [(set_attr "type" "arith,load,store")]) |
---|
721 | |
---|
722 | Note that we assume in the above example that arithmetic operations |
---|
723 | performed on quantities smaller than a machine word clobber the |
---|
724 | condition code since they will set the condition code to a value |
---|
725 | corresponding to the full-word result. |
---|
726 | |
---|
727 | |
---|
728 | File: gcc.info, Node: Insn Lengths, Next: Constant Attributes, Prev: Attr Example, Up: Insn Attributes |
---|
729 | |
---|
730 | Computing the Length of an Insn |
---|
731 | ------------------------------- |
---|
732 | |
---|
733 | For many machines, multiple types of branch instructions are |
---|
734 | provided, each for different length branch displacements. In most |
---|
735 | cases, the assembler will choose the correct instruction to use. |
---|
736 | However, when the assembler cannot do so, GCC can when a special |
---|
737 | attribute, the `length' attribute, is defined. This attribute must be |
---|
738 | defined to have numeric values by specifying a null string in its |
---|
739 | `define_attr'. |
---|
740 | |
---|
741 | In the case of the `length' attribute, two additional forms of |
---|
742 | arithmetic terms are allowed in test expressions: |
---|
743 | |
---|
744 | `(match_dup N)' |
---|
745 | This refers to the address of operand N of the current insn, which |
---|
746 | must be a `label_ref'. |
---|
747 | |
---|
748 | `(pc)' |
---|
749 | This refers to the address of the *current* insn. It might have |
---|
750 | been more consistent with other usage to make this the address of |
---|
751 | the *next* insn but this would be confusing because the length of |
---|
752 | the current insn is to be computed. |
---|
753 | |
---|
754 | For normal insns, the length will be determined by value of the |
---|
755 | `length' attribute. In the case of `addr_vec' and `addr_diff_vec' insn |
---|
756 | patterns, the length is computed as the number of vectors multiplied by |
---|
757 | the size of each vector. |
---|
758 | |
---|
759 | Lengths are measured in addressable storage units (bytes). |
---|
760 | |
---|
761 | The following macros can be used to refine the length computation: |
---|
762 | |
---|
763 | `FIRST_INSN_ADDRESS' |
---|
764 | When the `length' insn attribute is used, this macro specifies the |
---|
765 | value to be assigned to the address of the first insn in a |
---|
766 | function. If not specified, 0 is used. |
---|
767 | |
---|
768 | `ADJUST_INSN_LENGTH (INSN, LENGTH)' |
---|
769 | If defined, modifies the length assigned to instruction INSN as a |
---|
770 | function of the context in which it is used. LENGTH is an lvalue |
---|
771 | that contains the initially computed length of the insn and should |
---|
772 | be updated with the correct length of the insn. If updating is |
---|
773 | required, INSN must not be a varying-length insn. |
---|
774 | |
---|
775 | This macro will normally not be required. A case in which it is |
---|
776 | required is the ROMP. On this machine, the size of an `addr_vec' |
---|
777 | insn must be increased by two to compensate for the fact that |
---|
778 | alignment may be required. |
---|
779 | |
---|
780 | The routine that returns `get_attr_length' (the value of the |
---|
781 | `length' attribute) can be used by the output routine to determine the |
---|
782 | form of the branch instruction to be written, as the example below |
---|
783 | illustrates. |
---|
784 | |
---|
785 | As an example of the specification of variable-length branches, |
---|
786 | consider the IBM 360. If we adopt the convention that a register will |
---|
787 | be set to the starting address of a function, we can jump to labels |
---|
788 | within 4k of the start using a four-byte instruction. Otherwise, we |
---|
789 | need a six-byte sequence to load the address from memory and then |
---|
790 | branch to it. |
---|
791 | |
---|
792 | On such a machine, a pattern for a branch instruction might be |
---|
793 | specified as follows: |
---|
794 | |
---|
795 | (define_insn "jump" |
---|
796 | [(set (pc) |
---|
797 | (label_ref (match_operand 0 "" "")))] |
---|
798 | "" |
---|
799 | "* |
---|
800 | { |
---|
801 | return (get_attr_length (insn) == 4 |
---|
802 | ? \"b %l0\" : \"l r15,=a(%l0); br r15\"); |
---|
803 | }" |
---|
804 | [(set (attr "length") (if_then_else (lt (match_dup 0) (const_int 4096)) |
---|
805 | (const_int 4) |
---|
806 | (const_int 6)))]) |
---|
807 | |
---|
808 | |
---|
809 | File: gcc.info, Node: Constant Attributes, Next: Delay Slots, Prev: Insn Lengths, Up: Insn Attributes |
---|
810 | |
---|
811 | Constant Attributes |
---|
812 | ------------------- |
---|
813 | |
---|
814 | A special form of `define_attr', where the expression for the |
---|
815 | default value is a `const' expression, indicates an attribute that is |
---|
816 | constant for a given run of the compiler. Constant attributes may be |
---|
817 | used to specify which variety of processor is used. For example, |
---|
818 | |
---|
819 | (define_attr "cpu" "m88100,m88110,m88000" |
---|
820 | (const |
---|
821 | (cond [(symbol_ref "TARGET_88100") (const_string "m88100") |
---|
822 | (symbol_ref "TARGET_88110") (const_string "m88110")] |
---|
823 | (const_string "m88000")))) |
---|
824 | |
---|
825 | (define_attr "memory" "fast,slow" |
---|
826 | (const |
---|
827 | (if_then_else (symbol_ref "TARGET_FAST_MEM") |
---|
828 | (const_string "fast") |
---|
829 | (const_string "slow")))) |
---|
830 | |
---|
831 | The routine generated for constant attributes has no parameters as it |
---|
832 | does not depend on any particular insn. RTL expressions used to define |
---|
833 | the value of a constant attribute may use the `symbol_ref' form, but |
---|
834 | may not use either the `match_operand' form or `eq_attr' forms |
---|
835 | involving insn attributes. |
---|
836 | |
---|
837 | |
---|
838 | File: gcc.info, Node: Delay Slots, Next: Function Units, Prev: Constant Attributes, Up: Insn Attributes |
---|
839 | |
---|
840 | Delay Slot Scheduling |
---|
841 | --------------------- |
---|
842 | |
---|
843 | The insn attribute mechanism can be used to specify the requirements |
---|
844 | for delay slots, if any, on a target machine. An instruction is said to |
---|
845 | require a "delay slot" if some instructions that are physically after |
---|
846 | the instruction are executed as if they were located before it. |
---|
847 | Classic examples are branch and call instructions, which often execute |
---|
848 | the following instruction before the branch or call is performed. |
---|
849 | |
---|
850 | On some machines, conditional branch instructions can optionally |
---|
851 | "annul" instructions in the delay slot. This means that the |
---|
852 | instruction will not be executed for certain branch outcomes. Both |
---|
853 | instructions that annul if the branch is true and instructions that |
---|
854 | annul if the branch is false are supported. |
---|
855 | |
---|
856 | Delay slot scheduling differs from instruction scheduling in that |
---|
857 | determining whether an instruction needs a delay slot is dependent only |
---|
858 | on the type of instruction being generated, not on data flow between the |
---|
859 | instructions. See the next section for a discussion of data-dependent |
---|
860 | instruction scheduling. |
---|
861 | |
---|
862 | The requirement of an insn needing one or more delay slots is |
---|
863 | indicated via the `define_delay' expression. It has the following form: |
---|
864 | |
---|
865 | (define_delay TEST |
---|
866 | [DELAY-1 ANNUL-TRUE-1 ANNUL-FALSE-1 |
---|
867 | DELAY-2 ANNUL-TRUE-2 ANNUL-FALSE-2 |
---|
868 | ...]) |
---|
869 | |
---|
870 | TEST is an attribute test that indicates whether this `define_delay' |
---|
871 | applies to a particular insn. If so, the number of required delay |
---|
872 | slots is determined by the length of the vector specified as the second |
---|
873 | argument. An insn placed in delay slot N must satisfy attribute test |
---|
874 | DELAY-N. ANNUL-TRUE-N is an attribute test that specifies which insns |
---|
875 | may be annulled if the branch is true. Similarly, ANNUL-FALSE-N |
---|
876 | specifies which insns in the delay slot may be annulled if the branch |
---|
877 | is false. If annulling is not supported for that delay slot, `(nil)' |
---|
878 | should be coded. |
---|
879 | |
---|
880 | For example, in the common case where branch and call insns require |
---|
881 | a single delay slot, which may contain any insn other than a branch or |
---|
882 | call, the following would be placed in the `md' file: |
---|
883 | |
---|
884 | (define_delay (eq_attr "type" "branch,call") |
---|
885 | [(eq_attr "type" "!branch,call") (nil) (nil)]) |
---|
886 | |
---|
887 | Multiple `define_delay' expressions may be specified. In this case, |
---|
888 | each such expression specifies different delay slot requirements and |
---|
889 | there must be no insn for which tests in two `define_delay' expressions |
---|
890 | are both true. |
---|
891 | |
---|
892 | For example, if we have a machine that requires one delay slot for |
---|
893 | branches but two for calls, no delay slot can contain a branch or call |
---|
894 | insn, and any valid insn in the delay slot for the branch can be |
---|
895 | annulled if the branch is true, we might represent this as follows: |
---|
896 | |
---|
897 | (define_delay (eq_attr "type" "branch") |
---|
898 | [(eq_attr "type" "!branch,call") |
---|
899 | (eq_attr "type" "!branch,call") |
---|
900 | (nil)]) |
---|
901 | |
---|
902 | (define_delay (eq_attr "type" "call") |
---|
903 | [(eq_attr "type" "!branch,call") (nil) (nil) |
---|
904 | (eq_attr "type" "!branch,call") (nil) (nil)]) |
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905 | |
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906 | |
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907 | File: gcc.info, Node: Function Units, Prev: Delay Slots, Up: Insn Attributes |
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908 | |
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909 | Specifying Function Units |
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910 | ------------------------- |
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911 | |
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912 | On most RISC machines, there are instructions whose results are not |
---|
913 | available for a specific number of cycles. Common cases are |
---|
914 | instructions that load data from memory. On many machines, a pipeline |
---|
915 | stall will result if the data is referenced too soon after the load |
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916 | instruction. |
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917 | |
---|
918 | In addition, many newer microprocessors have multiple function |
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919 | units, usually one for integer and one for floating point, and often |
---|
920 | will incur pipeline stalls when a result that is needed is not yet |
---|
921 | ready. |
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922 | |
---|
923 | The descriptions in this section allow the specification of how much |
---|
924 | time must elapse between the execution of an instruction and the time |
---|
925 | when its result is used. It also allows specification of when the |
---|
926 | execution of an instruction will delay execution of similar instructions |
---|
927 | due to function unit conflicts. |
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928 | |
---|
929 | For the purposes of the specifications in this section, a machine is |
---|
930 | divided into "function units", each of which execute a specific class |
---|
931 | of instructions in first-in-first-out order. Function units that |
---|
932 | accept one instruction each cycle and allow a result to be used in the |
---|
933 | succeeding instruction (usually via forwarding) need not be specified. |
---|
934 | Classic RISC microprocessors will normally have a single function unit, |
---|
935 | which we can call `memory'. The newer "superscalar" processors will |
---|
936 | often have function units for floating point operations, usually at |
---|
937 | least a floating point adder and multiplier. |
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938 | |
---|
939 | Each usage of a function units by a class of insns is specified with |
---|
940 | a `define_function_unit' expression, which looks like this: |
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941 | |
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942 | (define_function_unit NAME MULTIPLICITY SIMULTANEITY |
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943 | TEST READY-DELAY ISSUE-DELAY |
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944 | [CONFLICT-LIST]) |
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945 | |
---|
946 | NAME is a string giving the name of the function unit. |
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947 | |
---|
948 | MULTIPLICITY is an integer specifying the number of identical units |
---|
949 | in the processor. If more than one unit is specified, they will be |
---|
950 | scheduled independently. Only truly independent units should be |
---|
951 | counted; a pipelined unit should be specified as a single unit. (The |
---|
952 | only common example of a machine that has multiple function units for a |
---|
953 | single instruction class that are truly independent and not pipelined |
---|
954 | are the two multiply and two increment units of the CDC 6600.) |
---|
955 | |
---|
956 | SIMULTANEITY specifies the maximum number of insns that can be |
---|
957 | executing in each instance of the function unit simultaneously or zero |
---|
958 | if the unit is pipelined and has no limit. |
---|
959 | |
---|
960 | All `define_function_unit' definitions referring to function unit |
---|
961 | NAME must have the same name and values for MULTIPLICITY and |
---|
962 | SIMULTANEITY. |
---|
963 | |
---|
964 | TEST is an attribute test that selects the insns we are describing |
---|
965 | in this definition. Note that an insn may use more than one function |
---|
966 | unit and a function unit may be specified in more than one |
---|
967 | `define_function_unit'. |
---|
968 | |
---|
969 | READY-DELAY is an integer that specifies the number of cycles after |
---|
970 | which the result of the instruction can be used without introducing any |
---|
971 | stalls. |
---|
972 | |
---|
973 | ISSUE-DELAY is an integer that specifies the number of cycles after |
---|
974 | the instruction matching the TEST expression begins using this unit |
---|
975 | until a subsequent instruction can begin. A cost of N indicates an N-1 |
---|
976 | cycle delay. A subsequent instruction may also be delayed if an |
---|
977 | earlier instruction has a longer READY-DELAY value. This blocking |
---|
978 | effect is computed using the SIMULTANEITY, READY-DELAY, ISSUE-DELAY, |
---|
979 | and CONFLICT-LIST terms. For a normal non-pipelined function unit, |
---|
980 | SIMULTANEITY is one, the unit is taken to block for the READY-DELAY |
---|
981 | cycles of the executing insn, and smaller values of ISSUE-DELAY are |
---|
982 | ignored. |
---|
983 | |
---|
984 | CONFLICT-LIST is an optional list giving detailed conflict costs for |
---|
985 | this unit. If specified, it is a list of condition test expressions to |
---|
986 | be applied to insns chosen to execute in NAME following the particular |
---|
987 | insn matching TEST that is already executing in NAME. For each insn in |
---|
988 | the list, ISSUE-DELAY specifies the conflict cost; for insns not in the |
---|
989 | list, the cost is zero. If not specified, CONFLICT-LIST defaults to |
---|
990 | all instructions that use the function unit. |
---|
991 | |
---|
992 | Typical uses of this vector are where a floating point function unit |
---|
993 | can pipeline either single- or double-precision operations, but not |
---|
994 | both, or where a memory unit can pipeline loads, but not stores, etc. |
---|
995 | |
---|
996 | As an example, consider a classic RISC machine where the result of a |
---|
997 | load instruction is not available for two cycles (a single "delay" |
---|
998 | instruction is required) and where only one load instruction can be |
---|
999 | executed simultaneously. This would be specified as: |
---|
1000 | |
---|
1001 | (define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 0) |
---|
1002 | |
---|
1003 | For the case of a floating point function unit that can pipeline |
---|
1004 | either single or double precision, but not both, the following could be |
---|
1005 | specified: |
---|
1006 | |
---|
1007 | (define_function_unit |
---|
1008 | "fp" 1 0 (eq_attr "type" "sp_fp") 4 4 [(eq_attr "type" "dp_fp")]) |
---|
1009 | (define_function_unit |
---|
1010 | "fp" 1 0 (eq_attr "type" "dp_fp") 4 4 [(eq_attr "type" "sp_fp")]) |
---|
1011 | |
---|
1012 | *Note:* The scheduler attempts to avoid function unit conflicts and |
---|
1013 | uses all the specifications in the `define_function_unit' expression. |
---|
1014 | It has recently come to our attention that these specifications may not |
---|
1015 | allow modeling of some of the newer "superscalar" processors that have |
---|
1016 | insns using multiple pipelined units. These insns will cause a |
---|
1017 | potential conflict for the second unit used during their execution and |
---|
1018 | there is no way of representing that conflict. We welcome any examples |
---|
1019 | of how function unit conflicts work in such processors and suggestions |
---|
1020 | for their representation. |
---|
1021 | |
---|
1022 | |
---|
1023 | File: gcc.info, Node: Target Macros, Next: Config, Prev: Machine Desc, Up: Top |
---|
1024 | |
---|
1025 | Target Description Macros |
---|
1026 | ************************* |
---|
1027 | |
---|
1028 | In addition to the file `MACHINE.md', a machine description includes |
---|
1029 | a C header file conventionally given the name `MACHINE.h'. This header |
---|
1030 | file defines numerous macros that convey the information about the |
---|
1031 | target machine that does not fit into the scheme of the `.md' file. |
---|
1032 | The file `tm.h' should be a link to `MACHINE.h'. The header file |
---|
1033 | `config.h' includes `tm.h' and most compiler source files include |
---|
1034 | `config.h'. |
---|
1035 | |
---|
1036 | * Menu: |
---|
1037 | |
---|
1038 | * Driver:: Controlling how the driver runs the compilation passes. |
---|
1039 | * Run-time Target:: Defining `-m' options like `-m68000' and `-m68020'. |
---|
1040 | * Storage Layout:: Defining sizes and alignments of data. |
---|
1041 | * Type Layout:: Defining sizes and properties of basic user data types. |
---|
1042 | * Registers:: Naming and describing the hardware registers. |
---|
1043 | * Register Classes:: Defining the classes of hardware registers. |
---|
1044 | * Stack and Calling:: Defining which way the stack grows and by how much. |
---|
1045 | * Varargs:: Defining the varargs macros. |
---|
1046 | * Trampolines:: Code set up at run time to enter a nested function. |
---|
1047 | * Library Calls:: Controlling how library routines are implicitly called. |
---|
1048 | * Addressing Modes:: Defining addressing modes valid for memory operands. |
---|
1049 | * Condition Code:: Defining how insns update the condition code. |
---|
1050 | * Costs:: Defining relative costs of different operations. |
---|
1051 | * Sections:: Dividing storage into text, data, and other sections. |
---|
1052 | * PIC:: Macros for position independent code. |
---|
1053 | * Assembler Format:: Defining how to write insns and pseudo-ops to output. |
---|
1054 | * Debugging Info:: Defining the format of debugging output. |
---|
1055 | * Cross-compilation:: Handling floating point for cross-compilers. |
---|
1056 | * Misc:: Everything else. |
---|
1057 | |
---|