1 | /* Allocate registers within a basic block, for GNU compiler. |
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2 | Copyright (C) 1987, 88, 91, 93, 94, 1995 Free Software Foundation, Inc. |
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3 | |
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4 | This file is part of GNU CC. |
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5 | |
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6 | GNU CC is free software; you can redistribute it and/or modify |
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7 | it under the terms of the GNU General Public License as published by |
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8 | the Free Software Foundation; either version 2, or (at your option) |
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9 | any later version. |
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10 | |
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11 | GNU CC is distributed in the hope that it will be useful, |
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12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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14 | GNU General Public License for more details. |
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15 | |
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16 | You should have received a copy of the GNU General Public License |
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17 | along with GNU CC; see the file COPYING. If not, write to |
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18 | the Free Software Foundation, 59 Temple Place - Suite 330, |
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19 | Boston, MA 02111-1307, USA. */ |
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20 | |
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21 | |
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22 | /* Allocation of hard register numbers to pseudo registers is done in |
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23 | two passes. In this pass we consider only regs that are born and |
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24 | die once within one basic block. We do this one basic block at a |
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25 | time. Then the next pass allocates the registers that remain. |
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26 | Two passes are used because this pass uses methods that work only |
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27 | on linear code, but that do a better job than the general methods |
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28 | used in global_alloc, and more quickly too. |
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29 | |
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30 | The assignments made are recorded in the vector reg_renumber |
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31 | whose space is allocated here. The rtl code itself is not altered. |
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32 | |
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33 | We assign each instruction in the basic block a number |
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34 | which is its order from the beginning of the block. |
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35 | Then we can represent the lifetime of a pseudo register with |
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36 | a pair of numbers, and check for conflicts easily. |
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37 | We can record the availability of hard registers with a |
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38 | HARD_REG_SET for each instruction. The HARD_REG_SET |
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39 | contains 0 or 1 for each hard reg. |
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40 | |
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41 | To avoid register shuffling, we tie registers together when one |
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42 | dies by being copied into another, or dies in an instruction that |
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43 | does arithmetic to produce another. The tied registers are |
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44 | allocated as one. Registers with different reg class preferences |
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45 | can never be tied unless the class preferred by one is a subclass |
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46 | of the one preferred by the other. |
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47 | |
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48 | Tying is represented with "quantity numbers". |
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49 | A non-tied register is given a new quantity number. |
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50 | Tied registers have the same quantity number. |
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51 | |
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52 | We have provision to exempt registers, even when they are contained |
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53 | within the block, that can be tied to others that are not contained in it. |
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54 | This is so that global_alloc could process them both and tie them then. |
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55 | But this is currently disabled since tying in global_alloc is not |
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56 | yet implemented. */ |
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57 | |
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58 | #include <stdio.h> |
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59 | #include "config.h" |
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60 | #include "rtl.h" |
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61 | #include "flags.h" |
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62 | #include "basic-block.h" |
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63 | #include "regs.h" |
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64 | #include "hard-reg-set.h" |
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65 | #include "insn-config.h" |
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66 | #include "recog.h" |
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67 | #include "output.h" |
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68 | |
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69 | /* Pseudos allocated here cannot be reallocated by global.c if the hard |
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70 | register is used as a spill register. So we don't allocate such pseudos |
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71 | here if their preferred class is likely to be used by spills. |
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72 | |
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73 | On most machines, the appropriate test is if the class has one |
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74 | register, so we default to that. */ |
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75 | |
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76 | #ifndef CLASS_LIKELY_SPILLED_P |
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77 | #define CLASS_LIKELY_SPILLED_P(CLASS) (reg_class_size[(int) (CLASS)] == 1) |
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78 | #endif |
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79 | |
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80 | /* Next quantity number available for allocation. */ |
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81 | |
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82 | static int next_qty; |
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83 | |
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84 | /* In all the following vectors indexed by quantity number. */ |
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85 | |
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86 | /* Element Q is the hard reg number chosen for quantity Q, |
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87 | or -1 if none was found. */ |
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88 | |
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89 | static short *qty_phys_reg; |
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90 | |
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91 | /* We maintain two hard register sets that indicate suggested hard registers |
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92 | for each quantity. The first, qty_phys_copy_sugg, contains hard registers |
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93 | that are tied to the quantity by a simple copy. The second contains all |
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94 | hard registers that are tied to the quantity via an arithmetic operation. |
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95 | |
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96 | The former register set is given priority for allocation. This tends to |
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97 | eliminate copy insns. */ |
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98 | |
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99 | /* Element Q is a set of hard registers that are suggested for quantity Q by |
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100 | copy insns. */ |
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101 | |
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102 | static HARD_REG_SET *qty_phys_copy_sugg; |
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103 | |
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104 | /* Element Q is a set of hard registers that are suggested for quantity Q by |
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105 | arithmetic insns. */ |
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106 | |
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107 | static HARD_REG_SET *qty_phys_sugg; |
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108 | |
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109 | /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */ |
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110 | |
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111 | static short *qty_phys_num_copy_sugg; |
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112 | |
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113 | /* Element Q is the number of suggested registers in qty_phys_sugg. */ |
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114 | |
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115 | static short *qty_phys_num_sugg; |
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116 | |
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117 | /* Element Q is the number of refs to quantity Q. */ |
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118 | |
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119 | static int *qty_n_refs; |
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120 | |
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121 | /* Element Q is a reg class contained in (smaller than) the |
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122 | preferred classes of all the pseudo regs that are tied in quantity Q. |
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123 | This is the preferred class for allocating that quantity. */ |
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124 | |
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125 | static enum reg_class *qty_min_class; |
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126 | |
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127 | /* Insn number (counting from head of basic block) |
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128 | where quantity Q was born. -1 if birth has not been recorded. */ |
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129 | |
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130 | static int *qty_birth; |
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131 | |
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132 | /* Insn number (counting from head of basic block) |
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133 | where quantity Q died. Due to the way tying is done, |
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134 | and the fact that we consider in this pass only regs that die but once, |
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135 | a quantity can die only once. Each quantity's life span |
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136 | is a set of consecutive insns. -1 if death has not been recorded. */ |
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137 | |
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138 | static int *qty_death; |
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139 | |
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140 | /* Number of words needed to hold the data in quantity Q. |
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141 | This depends on its machine mode. It is used for these purposes: |
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142 | 1. It is used in computing the relative importances of qtys, |
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143 | which determines the order in which we look for regs for them. |
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144 | 2. It is used in rules that prevent tying several registers of |
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145 | different sizes in a way that is geometrically impossible |
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146 | (see combine_regs). */ |
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147 | |
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148 | static int *qty_size; |
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149 | |
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150 | /* This holds the mode of the registers that are tied to qty Q, |
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151 | or VOIDmode if registers with differing modes are tied together. */ |
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152 | |
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153 | static enum machine_mode *qty_mode; |
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154 | |
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155 | /* Number of times a reg tied to qty Q lives across a CALL_INSN. */ |
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156 | |
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157 | static int *qty_n_calls_crossed; |
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158 | |
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159 | /* Register class within which we allocate qty Q if we can't get |
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160 | its preferred class. */ |
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161 | |
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162 | static enum reg_class *qty_alternate_class; |
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163 | |
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164 | /* Element Q is the SCRATCH expression for which this quantity is being |
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165 | allocated or 0 if this quantity is allocating registers. */ |
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166 | |
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167 | static rtx *qty_scratch_rtx; |
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168 | |
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169 | /* Element Q is nonzero if this quantity has been used in a SUBREG |
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170 | that changes its size. */ |
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171 | |
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172 | static char *qty_changes_size; |
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173 | |
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174 | /* Element Q is the register number of one pseudo register whose |
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175 | reg_qty value is Q, or -1 is this quantity is for a SCRATCH. This |
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176 | register should be the head of the chain maintained in reg_next_in_qty. */ |
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177 | |
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178 | static int *qty_first_reg; |
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179 | |
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180 | /* If (REG N) has been assigned a quantity number, is a register number |
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181 | of another register assigned the same quantity number, or -1 for the |
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182 | end of the chain. qty_first_reg point to the head of this chain. */ |
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183 | |
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184 | static int *reg_next_in_qty; |
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185 | |
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186 | /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg |
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187 | if it is >= 0, |
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188 | of -1 if this register cannot be allocated by local-alloc, |
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189 | or -2 if not known yet. |
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190 | |
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191 | Note that if we see a use or death of pseudo register N with |
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192 | reg_qty[N] == -2, register N must be local to the current block. If |
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193 | it were used in more than one block, we would have reg_qty[N] == -1. |
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194 | This relies on the fact that if reg_basic_block[N] is >= 0, register N |
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195 | will not appear in any other block. We save a considerable number of |
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196 | tests by exploiting this. |
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197 | |
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198 | If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not |
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199 | be referenced. */ |
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200 | |
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201 | static int *reg_qty; |
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202 | |
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203 | /* The offset (in words) of register N within its quantity. |
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204 | This can be nonzero if register N is SImode, and has been tied |
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205 | to a subreg of a DImode register. */ |
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206 | |
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207 | static char *reg_offset; |
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208 | |
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209 | /* Vector of substitutions of register numbers, |
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210 | used to map pseudo regs into hardware regs. |
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211 | This is set up as a result of register allocation. |
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212 | Element N is the hard reg assigned to pseudo reg N, |
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213 | or is -1 if no hard reg was assigned. |
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214 | If N is a hard reg number, element N is N. */ |
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215 | |
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216 | short *reg_renumber; |
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217 | |
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218 | /* Set of hard registers live at the current point in the scan |
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219 | of the instructions in a basic block. */ |
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220 | |
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221 | static HARD_REG_SET regs_live; |
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222 | |
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223 | /* Each set of hard registers indicates registers live at a particular |
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224 | point in the basic block. For N even, regs_live_at[N] says which |
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225 | hard registers are needed *after* insn N/2 (i.e., they may not |
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226 | conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1. |
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227 | |
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228 | If an object is to conflict with the inputs of insn J but not the |
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229 | outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly, |
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230 | if it is to conflict with the outputs of insn J but not the inputs of |
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231 | insn J + 1, it is said to die at index J*2 + 1. */ |
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232 | |
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233 | static HARD_REG_SET *regs_live_at; |
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234 | |
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235 | int *scratch_block; |
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236 | rtx *scratch_list; |
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237 | int scratch_list_length; |
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238 | static int scratch_index; |
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239 | |
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240 | /* Communicate local vars `insn_number' and `insn' |
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241 | from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */ |
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242 | static int this_insn_number; |
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243 | static rtx this_insn; |
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244 | |
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245 | static void alloc_qty PROTO((int, enum machine_mode, int, int)); |
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246 | static void alloc_qty_for_scratch PROTO((rtx, int, rtx, int, int)); |
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247 | static void validate_equiv_mem_from_store PROTO((rtx, rtx)); |
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248 | static int validate_equiv_mem PROTO((rtx, rtx, rtx)); |
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249 | static int memref_referenced_p PROTO((rtx, rtx)); |
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250 | static int memref_used_between_p PROTO((rtx, rtx, rtx)); |
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251 | static void optimize_reg_copy_1 PROTO((rtx, rtx, rtx)); |
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252 | static void optimize_reg_copy_2 PROTO((rtx, rtx, rtx)); |
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253 | static void update_equiv_regs PROTO((void)); |
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254 | static void block_alloc PROTO((int)); |
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255 | static int qty_sugg_compare PROTO((int, int)); |
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256 | static int qty_sugg_compare_1 PROTO((int *, int *)); |
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257 | static int qty_compare PROTO((int, int)); |
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258 | static int qty_compare_1 PROTO((int *, int *)); |
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259 | static int combine_regs PROTO((rtx, rtx, int, int, rtx, int)); |
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260 | static int reg_meets_class_p PROTO((int, enum reg_class)); |
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261 | static int reg_classes_overlap_p PROTO((enum reg_class, enum reg_class, |
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262 | int)); |
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263 | static void update_qty_class PROTO((int, int)); |
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264 | static void reg_is_set PROTO((rtx, rtx)); |
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265 | static void reg_is_born PROTO((rtx, int)); |
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266 | static void wipe_dead_reg PROTO((rtx, int)); |
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267 | static int find_free_reg PROTO((enum reg_class, enum machine_mode, |
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268 | int, int, int, int, int)); |
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269 | static void mark_life PROTO((int, enum machine_mode, int)); |
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270 | static void post_mark_life PROTO((int, enum machine_mode, int, int, int)); |
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271 | static int no_conflict_p PROTO((rtx, rtx, rtx)); |
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272 | static int requires_inout PROTO((char *)); |
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273 | |
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274 | /* Allocate a new quantity (new within current basic block) |
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275 | for register number REGNO which is born at index BIRTH |
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276 | within the block. MODE and SIZE are info on reg REGNO. */ |
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277 | |
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278 | static void |
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279 | alloc_qty (regno, mode, size, birth) |
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280 | int regno; |
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281 | enum machine_mode mode; |
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282 | int size, birth; |
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283 | { |
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284 | register int qty = next_qty++; |
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285 | |
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286 | reg_qty[regno] = qty; |
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287 | reg_offset[regno] = 0; |
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288 | reg_next_in_qty[regno] = -1; |
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289 | |
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290 | qty_first_reg[qty] = regno; |
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291 | qty_size[qty] = size; |
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292 | qty_mode[qty] = mode; |
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293 | qty_birth[qty] = birth; |
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294 | qty_n_calls_crossed[qty] = reg_n_calls_crossed[regno]; |
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295 | qty_min_class[qty] = reg_preferred_class (regno); |
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296 | qty_alternate_class[qty] = reg_alternate_class (regno); |
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297 | qty_n_refs[qty] = reg_n_refs[regno]; |
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298 | qty_changes_size[qty] = reg_changes_size[regno]; |
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299 | } |
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300 | |
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301 | /* Similar to `alloc_qty', but allocates a quantity for a SCRATCH rtx |
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302 | used as operand N in INSN. We assume here that the SCRATCH is used in |
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303 | a CLOBBER. */ |
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304 | |
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305 | static void |
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306 | alloc_qty_for_scratch (scratch, n, insn, insn_code_num, insn_number) |
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307 | rtx scratch; |
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308 | int n; |
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309 | rtx insn; |
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310 | int insn_code_num, insn_number; |
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311 | { |
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312 | register int qty; |
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313 | enum reg_class class; |
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314 | char *p, c; |
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315 | int i; |
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316 | |
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317 | #ifdef REGISTER_CONSTRAINTS |
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318 | /* If we haven't yet computed which alternative will be used, do so now. |
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319 | Then set P to the constraints for that alternative. */ |
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320 | if (which_alternative == -1) |
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321 | if (! constrain_operands (insn_code_num, 0)) |
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322 | return; |
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323 | |
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324 | for (p = insn_operand_constraint[insn_code_num][n], i = 0; |
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325 | *p && i < which_alternative; p++) |
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326 | if (*p == ',') |
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327 | i++; |
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328 | |
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329 | /* Compute the class required for this SCRATCH. If we don't need a |
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330 | register, the class will remain NO_REGS. If we guessed the alternative |
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331 | number incorrectly, reload will fix things up for us. */ |
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332 | |
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333 | class = NO_REGS; |
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334 | while ((c = *p++) != '\0' && c != ',') |
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335 | switch (c) |
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336 | { |
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337 | case '=': case '+': case '?': |
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338 | case '#': case '&': case '!': |
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339 | case '*': case '%': |
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340 | case '0': case '1': case '2': case '3': case '4': |
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341 | case 'm': case '<': case '>': case 'V': case 'o': |
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342 | case 'E': case 'F': case 'G': case 'H': |
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343 | case 's': case 'i': case 'n': |
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344 | case 'I': case 'J': case 'K': case 'L': |
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345 | case 'M': case 'N': case 'O': case 'P': |
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346 | #ifdef EXTRA_CONSTRAINT |
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347 | case 'Q': case 'R': case 'S': case 'T': case 'U': |
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348 | #endif |
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349 | case 'p': |
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350 | /* These don't say anything we care about. */ |
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351 | break; |
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352 | |
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353 | case 'X': |
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354 | /* We don't need to allocate this SCRATCH. */ |
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355 | return; |
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356 | |
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357 | case 'g': case 'r': |
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358 | class = reg_class_subunion[(int) class][(int) GENERAL_REGS]; |
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359 | break; |
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360 | |
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361 | default: |
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362 | class |
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363 | = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER (c)]; |
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364 | break; |
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365 | } |
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366 | |
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367 | if (class == NO_REGS) |
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368 | return; |
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369 | |
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370 | #else /* REGISTER_CONSTRAINTS */ |
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371 | |
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372 | class = GENERAL_REGS; |
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373 | #endif |
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374 | |
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375 | |
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376 | qty = next_qty++; |
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377 | |
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378 | qty_first_reg[qty] = -1; |
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379 | qty_scratch_rtx[qty] = scratch; |
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380 | qty_size[qty] = GET_MODE_SIZE (GET_MODE (scratch)); |
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381 | qty_mode[qty] = GET_MODE (scratch); |
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382 | qty_birth[qty] = 2 * insn_number - 1; |
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383 | qty_death[qty] = 2 * insn_number + 1; |
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384 | qty_n_calls_crossed[qty] = 0; |
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385 | qty_min_class[qty] = class; |
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386 | qty_alternate_class[qty] = NO_REGS; |
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387 | qty_n_refs[qty] = 1; |
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388 | qty_changes_size[qty] = 0; |
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389 | } |
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390 | |
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391 | /* Main entry point of this file. */ |
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392 | |
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393 | void |
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394 | local_alloc () |
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395 | { |
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396 | register int b, i; |
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397 | int max_qty; |
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398 | |
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399 | /* Leaf functions and non-leaf functions have different needs. |
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400 | If defined, let the machine say what kind of ordering we |
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401 | should use. */ |
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402 | #ifdef ORDER_REGS_FOR_LOCAL_ALLOC |
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403 | ORDER_REGS_FOR_LOCAL_ALLOC; |
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404 | #endif |
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405 | |
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406 | /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected |
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407 | registers. */ |
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408 | update_equiv_regs (); |
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409 | |
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410 | /* This sets the maximum number of quantities we can have. Quantity |
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411 | numbers start at zero and we can have one for each pseudo plus the |
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412 | number of SCRATCHes in the largest block, in the worst case. */ |
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413 | max_qty = (max_regno - FIRST_PSEUDO_REGISTER) + max_scratch; |
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414 | |
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415 | /* Allocate vectors of temporary data. |
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416 | See the declarations of these variables, above, |
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417 | for what they mean. */ |
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418 | |
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419 | /* There can be up to MAX_SCRATCH * N_BASIC_BLOCKS SCRATCHes to allocate. |
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420 | Instead of allocating this much memory from now until the end of |
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421 | reload, only allocate space for MAX_QTY SCRATCHes. If there are more |
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422 | reload will allocate them. */ |
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423 | |
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424 | scratch_list_length = max_qty; |
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425 | scratch_list = (rtx *) xmalloc (scratch_list_length * sizeof (rtx)); |
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426 | bzero ((char *) scratch_list, scratch_list_length * sizeof (rtx)); |
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427 | scratch_block = (int *) xmalloc (scratch_list_length * sizeof (int)); |
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428 | bzero ((char *) scratch_block, scratch_list_length * sizeof (int)); |
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429 | scratch_index = 0; |
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430 | |
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431 | qty_phys_reg = (short *) alloca (max_qty * sizeof (short)); |
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432 | qty_phys_copy_sugg |
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433 | = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET)); |
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434 | qty_phys_num_copy_sugg = (short *) alloca (max_qty * sizeof (short)); |
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435 | qty_phys_sugg = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET)); |
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436 | qty_phys_num_sugg = (short *) alloca (max_qty * sizeof (short)); |
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437 | qty_birth = (int *) alloca (max_qty * sizeof (int)); |
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438 | qty_death = (int *) alloca (max_qty * sizeof (int)); |
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439 | qty_scratch_rtx = (rtx *) alloca (max_qty * sizeof (rtx)); |
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440 | qty_first_reg = (int *) alloca (max_qty * sizeof (int)); |
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441 | qty_size = (int *) alloca (max_qty * sizeof (int)); |
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442 | qty_mode |
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443 | = (enum machine_mode *) alloca (max_qty * sizeof (enum machine_mode)); |
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444 | qty_n_calls_crossed = (int *) alloca (max_qty * sizeof (int)); |
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445 | qty_min_class |
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446 | = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class)); |
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447 | qty_alternate_class |
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448 | = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class)); |
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449 | qty_n_refs = (int *) alloca (max_qty * sizeof (int)); |
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450 | qty_changes_size = (char *) alloca (max_qty * sizeof (char)); |
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451 | |
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452 | reg_qty = (int *) alloca (max_regno * sizeof (int)); |
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453 | reg_offset = (char *) alloca (max_regno * sizeof (char)); |
---|
454 | reg_next_in_qty = (int *) alloca (max_regno * sizeof (int)); |
---|
455 | |
---|
456 | reg_renumber = (short *) oballoc (max_regno * sizeof (short)); |
---|
457 | for (i = 0; i < max_regno; i++) |
---|
458 | reg_renumber[i] = -1; |
---|
459 | |
---|
460 | /* Determine which pseudo-registers can be allocated by local-alloc. |
---|
461 | In general, these are the registers used only in a single block and |
---|
462 | which only die once. However, if a register's preferred class has only |
---|
463 | a few entries, don't allocate this register here unless it is preferred |
---|
464 | or nothing since retry_global_alloc won't be able to move it to |
---|
465 | GENERAL_REGS if a reload register of this class is needed. |
---|
466 | |
---|
467 | We need not be concerned with which block actually uses the register |
---|
468 | since we will never see it outside that block. */ |
---|
469 | |
---|
470 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) |
---|
471 | { |
---|
472 | if (reg_basic_block[i] >= 0 && reg_n_deaths[i] == 1 |
---|
473 | && (reg_alternate_class (i) == NO_REGS |
---|
474 | || ! CLASS_LIKELY_SPILLED_P (reg_preferred_class (i)))) |
---|
475 | reg_qty[i] = -2; |
---|
476 | else |
---|
477 | reg_qty[i] = -1; |
---|
478 | } |
---|
479 | |
---|
480 | /* Force loop below to initialize entire quantity array. */ |
---|
481 | next_qty = max_qty; |
---|
482 | |
---|
483 | /* Allocate each block's local registers, block by block. */ |
---|
484 | |
---|
485 | for (b = 0; b < n_basic_blocks; b++) |
---|
486 | { |
---|
487 | /* NEXT_QTY indicates which elements of the `qty_...' |
---|
488 | vectors might need to be initialized because they were used |
---|
489 | for the previous block; it is set to the entire array before |
---|
490 | block 0. Initialize those, with explicit loop if there are few, |
---|
491 | else with bzero and bcopy. Do not initialize vectors that are |
---|
492 | explicit set by `alloc_qty'. */ |
---|
493 | |
---|
494 | if (next_qty < 6) |
---|
495 | { |
---|
496 | for (i = 0; i < next_qty; i++) |
---|
497 | { |
---|
498 | qty_scratch_rtx[i] = 0; |
---|
499 | CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]); |
---|
500 | qty_phys_num_copy_sugg[i] = 0; |
---|
501 | CLEAR_HARD_REG_SET (qty_phys_sugg[i]); |
---|
502 | qty_phys_num_sugg[i] = 0; |
---|
503 | } |
---|
504 | } |
---|
505 | else |
---|
506 | { |
---|
507 | #define CLEAR(vector) \ |
---|
508 | bzero ((char *) (vector), (sizeof (*(vector))) * next_qty); |
---|
509 | |
---|
510 | CLEAR (qty_scratch_rtx); |
---|
511 | CLEAR (qty_phys_copy_sugg); |
---|
512 | CLEAR (qty_phys_num_copy_sugg); |
---|
513 | CLEAR (qty_phys_sugg); |
---|
514 | CLEAR (qty_phys_num_sugg); |
---|
515 | } |
---|
516 | |
---|
517 | next_qty = 0; |
---|
518 | |
---|
519 | block_alloc (b); |
---|
520 | #ifdef USE_C_ALLOCA |
---|
521 | alloca (0); |
---|
522 | #endif |
---|
523 | } |
---|
524 | } |
---|
525 | |
---|
526 | /* Depth of loops we are in while in update_equiv_regs. */ |
---|
527 | static int loop_depth; |
---|
528 | |
---|
529 | /* Used for communication between the following two functions: contains |
---|
530 | a MEM that we wish to ensure remains unchanged. */ |
---|
531 | static rtx equiv_mem; |
---|
532 | |
---|
533 | /* Set nonzero if EQUIV_MEM is modified. */ |
---|
534 | static int equiv_mem_modified; |
---|
535 | |
---|
536 | /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified. |
---|
537 | Called via note_stores. */ |
---|
538 | |
---|
539 | static void |
---|
540 | validate_equiv_mem_from_store (dest, set) |
---|
541 | rtx dest; |
---|
542 | rtx set; |
---|
543 | { |
---|
544 | if ((GET_CODE (dest) == REG |
---|
545 | && reg_overlap_mentioned_p (dest, equiv_mem)) |
---|
546 | || (GET_CODE (dest) == MEM |
---|
547 | && true_dependence (dest, equiv_mem))) |
---|
548 | equiv_mem_modified = 1; |
---|
549 | } |
---|
550 | |
---|
551 | /* Verify that no store between START and the death of REG invalidates |
---|
552 | MEMREF. MEMREF is invalidated by modifying a register used in MEMREF, |
---|
553 | by storing into an overlapping memory location, or with a non-const |
---|
554 | CALL_INSN. |
---|
555 | |
---|
556 | Return 1 if MEMREF remains valid. */ |
---|
557 | |
---|
558 | static int |
---|
559 | validate_equiv_mem (start, reg, memref) |
---|
560 | rtx start; |
---|
561 | rtx reg; |
---|
562 | rtx memref; |
---|
563 | { |
---|
564 | rtx insn; |
---|
565 | rtx note; |
---|
566 | |
---|
567 | equiv_mem = memref; |
---|
568 | equiv_mem_modified = 0; |
---|
569 | |
---|
570 | /* If the memory reference has side effects or is volatile, it isn't a |
---|
571 | valid equivalence. */ |
---|
572 | if (side_effects_p (memref)) |
---|
573 | return 0; |
---|
574 | |
---|
575 | for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn)) |
---|
576 | { |
---|
577 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') |
---|
578 | continue; |
---|
579 | |
---|
580 | if (find_reg_note (insn, REG_DEAD, reg)) |
---|
581 | return 1; |
---|
582 | |
---|
583 | if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref) |
---|
584 | && ! CONST_CALL_P (insn)) |
---|
585 | return 0; |
---|
586 | |
---|
587 | note_stores (PATTERN (insn), validate_equiv_mem_from_store); |
---|
588 | |
---|
589 | /* If a register mentioned in MEMREF is modified via an |
---|
590 | auto-increment, we lose the equivalence. Do the same if one |
---|
591 | dies; although we could extend the life, it doesn't seem worth |
---|
592 | the trouble. */ |
---|
593 | |
---|
594 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) |
---|
595 | if ((REG_NOTE_KIND (note) == REG_INC |
---|
596 | || REG_NOTE_KIND (note) == REG_DEAD) |
---|
597 | && GET_CODE (XEXP (note, 0)) == REG |
---|
598 | && reg_overlap_mentioned_p (XEXP (note, 0), memref)) |
---|
599 | return 0; |
---|
600 | } |
---|
601 | |
---|
602 | return 0; |
---|
603 | } |
---|
604 | |
---|
605 | /* TRUE if X references a memory location that would be affected by a store |
---|
606 | to MEMREF. */ |
---|
607 | |
---|
608 | static int |
---|
609 | memref_referenced_p (memref, x) |
---|
610 | rtx x; |
---|
611 | rtx memref; |
---|
612 | { |
---|
613 | int i, j; |
---|
614 | char *fmt; |
---|
615 | enum rtx_code code = GET_CODE (x); |
---|
616 | |
---|
617 | switch (code) |
---|
618 | { |
---|
619 | case REG: |
---|
620 | case CONST_INT: |
---|
621 | case CONST: |
---|
622 | case LABEL_REF: |
---|
623 | case SYMBOL_REF: |
---|
624 | case CONST_DOUBLE: |
---|
625 | case PC: |
---|
626 | case CC0: |
---|
627 | case HIGH: |
---|
628 | case LO_SUM: |
---|
629 | return 0; |
---|
630 | |
---|
631 | case MEM: |
---|
632 | if (true_dependence (memref, x)) |
---|
633 | return 1; |
---|
634 | break; |
---|
635 | |
---|
636 | case SET: |
---|
637 | /* If we are setting a MEM, it doesn't count (its address does), but any |
---|
638 | other SET_DEST that has a MEM in it is referencing the MEM. */ |
---|
639 | if (GET_CODE (SET_DEST (x)) == MEM) |
---|
640 | { |
---|
641 | if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0))) |
---|
642 | return 1; |
---|
643 | } |
---|
644 | else if (memref_referenced_p (memref, SET_DEST (x))) |
---|
645 | return 1; |
---|
646 | |
---|
647 | return memref_referenced_p (memref, SET_SRC (x)); |
---|
648 | } |
---|
649 | |
---|
650 | fmt = GET_RTX_FORMAT (code); |
---|
651 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
---|
652 | switch (fmt[i]) |
---|
653 | { |
---|
654 | case 'e': |
---|
655 | if (memref_referenced_p (memref, XEXP (x, i))) |
---|
656 | return 1; |
---|
657 | break; |
---|
658 | case 'E': |
---|
659 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
---|
660 | if (memref_referenced_p (memref, XVECEXP (x, i, j))) |
---|
661 | return 1; |
---|
662 | break; |
---|
663 | } |
---|
664 | |
---|
665 | return 0; |
---|
666 | } |
---|
667 | |
---|
668 | /* TRUE if some insn in the range (START, END] references a memory location |
---|
669 | that would be affected by a store to MEMREF. */ |
---|
670 | |
---|
671 | static int |
---|
672 | memref_used_between_p (memref, start, end) |
---|
673 | rtx memref; |
---|
674 | rtx start; |
---|
675 | rtx end; |
---|
676 | { |
---|
677 | rtx insn; |
---|
678 | |
---|
679 | for (insn = NEXT_INSN (start); insn != NEXT_INSN (end); |
---|
680 | insn = NEXT_INSN (insn)) |
---|
681 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' |
---|
682 | && memref_referenced_p (memref, PATTERN (insn))) |
---|
683 | return 1; |
---|
684 | |
---|
685 | return 0; |
---|
686 | } |
---|
687 | |
---|
688 | /* INSN is a copy from SRC to DEST, both registers, and SRC does not die |
---|
689 | in INSN. |
---|
690 | |
---|
691 | Search forward to see if SRC dies before either it or DEST is modified, |
---|
692 | but don't scan past the end of a basic block. If so, we can replace SRC |
---|
693 | with DEST and let SRC die in INSN. |
---|
694 | |
---|
695 | This will reduce the number of registers live in that range and may enable |
---|
696 | DEST to be tied to SRC, thus often saving one register in addition to a |
---|
697 | register-register copy. */ |
---|
698 | |
---|
699 | static void |
---|
700 | optimize_reg_copy_1 (insn, dest, src) |
---|
701 | rtx insn; |
---|
702 | rtx dest; |
---|
703 | rtx src; |
---|
704 | { |
---|
705 | rtx p, q; |
---|
706 | rtx note; |
---|
707 | rtx dest_death = 0; |
---|
708 | int sregno = REGNO (src); |
---|
709 | int dregno = REGNO (dest); |
---|
710 | |
---|
711 | if (sregno == dregno |
---|
712 | #ifdef SMALL_REGISTER_CLASSES |
---|
713 | /* We don't want to mess with hard regs if register classes are small. */ |
---|
714 | || sregno < FIRST_PSEUDO_REGISTER || dregno < FIRST_PSEUDO_REGISTER |
---|
715 | #endif |
---|
716 | /* We don't see all updates to SP if they are in an auto-inc memory |
---|
717 | reference, so we must disallow this optimization on them. */ |
---|
718 | || sregno == STACK_POINTER_REGNUM || dregno == STACK_POINTER_REGNUM) |
---|
719 | return; |
---|
720 | |
---|
721 | for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) |
---|
722 | { |
---|
723 | if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN |
---|
724 | || (GET_CODE (p) == NOTE |
---|
725 | && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG |
---|
726 | || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END))) |
---|
727 | break; |
---|
728 | |
---|
729 | if (GET_RTX_CLASS (GET_CODE (p)) != 'i') |
---|
730 | continue; |
---|
731 | |
---|
732 | if (reg_set_p (src, p) || reg_set_p (dest, p) |
---|
733 | /* Don't change a USE of a register. */ |
---|
734 | || (GET_CODE (PATTERN (p)) == USE |
---|
735 | && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0)))) |
---|
736 | break; |
---|
737 | |
---|
738 | /* See if all of SRC dies in P. This test is slightly more |
---|
739 | conservative than it needs to be. */ |
---|
740 | if ((note = find_regno_note (p, REG_DEAD, sregno)) != 0 |
---|
741 | && GET_MODE (XEXP (note, 0)) == GET_MODE (src)) |
---|
742 | { |
---|
743 | int failed = 0; |
---|
744 | int length = 0; |
---|
745 | int d_length = 0; |
---|
746 | int n_calls = 0; |
---|
747 | int d_n_calls = 0; |
---|
748 | |
---|
749 | /* We can do the optimization. Scan forward from INSN again, |
---|
750 | replacing regs as we go. Set FAILED if a replacement can't |
---|
751 | be done. In that case, we can't move the death note for SRC. |
---|
752 | This should be rare. */ |
---|
753 | |
---|
754 | /* Set to stop at next insn. */ |
---|
755 | for (q = next_real_insn (insn); |
---|
756 | q != next_real_insn (p); |
---|
757 | q = next_real_insn (q)) |
---|
758 | { |
---|
759 | if (reg_overlap_mentioned_p (src, PATTERN (q))) |
---|
760 | { |
---|
761 | /* If SRC is a hard register, we might miss some |
---|
762 | overlapping registers with validate_replace_rtx, |
---|
763 | so we would have to undo it. We can't if DEST is |
---|
764 | present in the insn, so fail in that combination |
---|
765 | of cases. */ |
---|
766 | if (sregno < FIRST_PSEUDO_REGISTER |
---|
767 | && reg_mentioned_p (dest, PATTERN (q))) |
---|
768 | failed = 1; |
---|
769 | |
---|
770 | /* Replace all uses and make sure that the register |
---|
771 | isn't still present. */ |
---|
772 | else if (validate_replace_rtx (src, dest, q) |
---|
773 | && (sregno >= FIRST_PSEUDO_REGISTER |
---|
774 | || ! reg_overlap_mentioned_p (src, |
---|
775 | PATTERN (q)))) |
---|
776 | { |
---|
777 | /* We assume that a register is used exactly once per |
---|
778 | insn in the updates below. If this is not correct, |
---|
779 | no great harm is done. */ |
---|
780 | if (sregno >= FIRST_PSEUDO_REGISTER) |
---|
781 | reg_n_refs[sregno] -= loop_depth; |
---|
782 | if (dregno >= FIRST_PSEUDO_REGISTER) |
---|
783 | reg_n_refs[dregno] += loop_depth; |
---|
784 | } |
---|
785 | else |
---|
786 | { |
---|
787 | validate_replace_rtx (dest, src, q); |
---|
788 | failed = 1; |
---|
789 | } |
---|
790 | } |
---|
791 | |
---|
792 | /* Count the insns and CALL_INSNs passed. If we passed the |
---|
793 | death note of DEST, show increased live length. */ |
---|
794 | length++; |
---|
795 | if (dest_death) |
---|
796 | d_length++; |
---|
797 | |
---|
798 | /* If the insn in which SRC dies is a CALL_INSN, don't count it |
---|
799 | as a call that has been crossed. Otherwise, count it. */ |
---|
800 | if (q != p && GET_CODE (q) == CALL_INSN) |
---|
801 | { |
---|
802 | n_calls++; |
---|
803 | if (dest_death) |
---|
804 | d_n_calls++; |
---|
805 | } |
---|
806 | |
---|
807 | /* If DEST dies here, remove the death note and save it for |
---|
808 | later. Make sure ALL of DEST dies here; again, this is |
---|
809 | overly conservative. */ |
---|
810 | if (dest_death == 0 |
---|
811 | && (dest_death = find_regno_note (q, REG_DEAD, dregno)) != 0 |
---|
812 | && GET_MODE (XEXP (dest_death, 0)) == GET_MODE (dest)) |
---|
813 | remove_note (q, dest_death); |
---|
814 | } |
---|
815 | |
---|
816 | if (! failed) |
---|
817 | { |
---|
818 | if (sregno >= FIRST_PSEUDO_REGISTER) |
---|
819 | { |
---|
820 | reg_live_length[sregno] -= length; |
---|
821 | /* reg_live_length is only an approximation after combine |
---|
822 | if sched is not run, so make sure that we still have |
---|
823 | a reasonable value. */ |
---|
824 | if (reg_live_length[sregno] < 2) |
---|
825 | reg_live_length[sregno] = 2; |
---|
826 | reg_n_calls_crossed[sregno] -= n_calls; |
---|
827 | } |
---|
828 | |
---|
829 | if (dregno >= FIRST_PSEUDO_REGISTER) |
---|
830 | { |
---|
831 | reg_live_length[dregno] += d_length; |
---|
832 | reg_n_calls_crossed[dregno] += d_n_calls; |
---|
833 | } |
---|
834 | |
---|
835 | /* Move death note of SRC from P to INSN. */ |
---|
836 | remove_note (p, note); |
---|
837 | XEXP (note, 1) = REG_NOTES (insn); |
---|
838 | REG_NOTES (insn) = note; |
---|
839 | } |
---|
840 | |
---|
841 | /* Put death note of DEST on P if we saw it die. */ |
---|
842 | if (dest_death) |
---|
843 | { |
---|
844 | XEXP (dest_death, 1) = REG_NOTES (p); |
---|
845 | REG_NOTES (p) = dest_death; |
---|
846 | } |
---|
847 | |
---|
848 | return; |
---|
849 | } |
---|
850 | |
---|
851 | /* If SRC is a hard register which is set or killed in some other |
---|
852 | way, we can't do this optimization. */ |
---|
853 | else if (sregno < FIRST_PSEUDO_REGISTER |
---|
854 | && dead_or_set_p (p, src)) |
---|
855 | break; |
---|
856 | } |
---|
857 | } |
---|
858 | |
---|
859 | /* INSN is a copy of SRC to DEST, in which SRC dies. See if we now have |
---|
860 | a sequence of insns that modify DEST followed by an insn that sets |
---|
861 | SRC to DEST in which DEST dies, with no prior modification of DEST. |
---|
862 | (There is no need to check if the insns in between actually modify |
---|
863 | DEST. We should not have cases where DEST is not modified, but |
---|
864 | the optimization is safe if no such modification is detected.) |
---|
865 | In that case, we can replace all uses of DEST, starting with INSN and |
---|
866 | ending with the set of SRC to DEST, with SRC. We do not do this |
---|
867 | optimization if a CALL_INSN is crossed unless SRC already crosses a |
---|
868 | call. |
---|
869 | |
---|
870 | It is assumed that DEST and SRC are pseudos; it is too complicated to do |
---|
871 | this for hard registers since the substitutions we may make might fail. */ |
---|
872 | |
---|
873 | static void |
---|
874 | optimize_reg_copy_2 (insn, dest, src) |
---|
875 | rtx insn; |
---|
876 | rtx dest; |
---|
877 | rtx src; |
---|
878 | { |
---|
879 | rtx p, q; |
---|
880 | rtx set; |
---|
881 | int sregno = REGNO (src); |
---|
882 | int dregno = REGNO (dest); |
---|
883 | |
---|
884 | for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) |
---|
885 | { |
---|
886 | if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN |
---|
887 | || (GET_CODE (p) == NOTE |
---|
888 | && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG |
---|
889 | || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END))) |
---|
890 | break; |
---|
891 | |
---|
892 | if (GET_RTX_CLASS (GET_CODE (p)) != 'i') |
---|
893 | continue; |
---|
894 | |
---|
895 | set = single_set (p); |
---|
896 | if (set && SET_SRC (set) == dest && SET_DEST (set) == src |
---|
897 | && find_reg_note (p, REG_DEAD, dest)) |
---|
898 | { |
---|
899 | /* We can do the optimization. Scan forward from INSN again, |
---|
900 | replacing regs as we go. */ |
---|
901 | |
---|
902 | /* Set to stop at next insn. */ |
---|
903 | for (q = insn; q != NEXT_INSN (p); q = NEXT_INSN (q)) |
---|
904 | if (GET_RTX_CLASS (GET_CODE (q)) == 'i') |
---|
905 | { |
---|
906 | if (reg_mentioned_p (dest, PATTERN (q))) |
---|
907 | { |
---|
908 | PATTERN (q) = replace_rtx (PATTERN (q), dest, src); |
---|
909 | |
---|
910 | /* We assume that a register is used exactly once per |
---|
911 | insn in the updates below. If this is not correct, |
---|
912 | no great harm is done. */ |
---|
913 | reg_n_refs[dregno] -= loop_depth; |
---|
914 | reg_n_refs[sregno] += loop_depth; |
---|
915 | } |
---|
916 | |
---|
917 | |
---|
918 | if (GET_CODE (q) == CALL_INSN) |
---|
919 | { |
---|
920 | reg_n_calls_crossed[dregno]--; |
---|
921 | reg_n_calls_crossed[sregno]++; |
---|
922 | } |
---|
923 | } |
---|
924 | |
---|
925 | remove_note (p, find_reg_note (p, REG_DEAD, dest)); |
---|
926 | reg_n_deaths[dregno]--; |
---|
927 | remove_note (insn, find_reg_note (insn, REG_DEAD, src)); |
---|
928 | reg_n_deaths[sregno]--; |
---|
929 | return; |
---|
930 | } |
---|
931 | |
---|
932 | if (reg_set_p (src, p) |
---|
933 | || (GET_CODE (p) == CALL_INSN && reg_n_calls_crossed[sregno] == 0)) |
---|
934 | break; |
---|
935 | } |
---|
936 | } |
---|
937 | |
---|
938 | /* Find registers that are equivalent to a single value throughout the |
---|
939 | compilation (either because they can be referenced in memory or are set once |
---|
940 | from a single constant). Lower their priority for a register. |
---|
941 | |
---|
942 | If such a register is only referenced once, try substituting its value |
---|
943 | into the using insn. If it succeeds, we can eliminate the register |
---|
944 | completely. */ |
---|
945 | |
---|
946 | static void |
---|
947 | update_equiv_regs () |
---|
948 | { |
---|
949 | rtx *reg_equiv_init_insn = (rtx *) alloca (max_regno * sizeof (rtx *)); |
---|
950 | rtx *reg_equiv_replacement = (rtx *) alloca (max_regno * sizeof (rtx *)); |
---|
951 | rtx insn; |
---|
952 | |
---|
953 | bzero ((char *) reg_equiv_init_insn, max_regno * sizeof (rtx *)); |
---|
954 | bzero ((char *) reg_equiv_replacement, max_regno * sizeof (rtx *)); |
---|
955 | |
---|
956 | init_alias_analysis (); |
---|
957 | |
---|
958 | loop_depth = 1; |
---|
959 | |
---|
960 | /* Scan the insns and find which registers have equivalences. Do this |
---|
961 | in a separate scan of the insns because (due to -fcse-follow-jumps) |
---|
962 | a register can be set below its use. */ |
---|
963 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
---|
964 | { |
---|
965 | rtx note; |
---|
966 | rtx set = single_set (insn); |
---|
967 | rtx dest; |
---|
968 | int regno; |
---|
969 | |
---|
970 | if (GET_CODE (insn) == NOTE) |
---|
971 | { |
---|
972 | if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) |
---|
973 | loop_depth++; |
---|
974 | else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) |
---|
975 | loop_depth--; |
---|
976 | } |
---|
977 | |
---|
978 | /* If this insn contains more (or less) than a single SET, ignore it. */ |
---|
979 | if (set == 0) |
---|
980 | continue; |
---|
981 | |
---|
982 | dest = SET_DEST (set); |
---|
983 | |
---|
984 | /* If this sets a MEM to the contents of a REG that is only used |
---|
985 | in a single basic block, see if the register is always equivalent |
---|
986 | to that memory location and if moving the store from INSN to the |
---|
987 | insn that set REG is safe. If so, put a REG_EQUIV note on the |
---|
988 | initializing insn. */ |
---|
989 | |
---|
990 | if (GET_CODE (dest) == MEM && GET_CODE (SET_SRC (set)) == REG |
---|
991 | && (regno = REGNO (SET_SRC (set))) >= FIRST_PSEUDO_REGISTER |
---|
992 | && reg_basic_block[regno] >= 0 |
---|
993 | && reg_equiv_init_insn[regno] != 0 |
---|
994 | && validate_equiv_mem (reg_equiv_init_insn[regno], SET_SRC (set), |
---|
995 | dest) |
---|
996 | && ! memref_used_between_p (SET_DEST (set), |
---|
997 | reg_equiv_init_insn[regno], insn)) |
---|
998 | REG_NOTES (reg_equiv_init_insn[regno]) |
---|
999 | = gen_rtx (EXPR_LIST, REG_EQUIV, dest, |
---|
1000 | REG_NOTES (reg_equiv_init_insn[regno])); |
---|
1001 | |
---|
1002 | /* If this is a register-register copy where SRC is not dead, see if we |
---|
1003 | can optimize it. */ |
---|
1004 | if (flag_expensive_optimizations && GET_CODE (dest) == REG |
---|
1005 | && GET_CODE (SET_SRC (set)) == REG |
---|
1006 | && ! find_reg_note (insn, REG_DEAD, SET_SRC (set))) |
---|
1007 | optimize_reg_copy_1 (insn, dest, SET_SRC (set)); |
---|
1008 | |
---|
1009 | /* Similarly for a pseudo-pseudo copy when SRC is dead. */ |
---|
1010 | else if (flag_expensive_optimizations && GET_CODE (dest) == REG |
---|
1011 | && REGNO (dest) >= FIRST_PSEUDO_REGISTER |
---|
1012 | && GET_CODE (SET_SRC (set)) == REG |
---|
1013 | && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER |
---|
1014 | && find_reg_note (insn, REG_DEAD, SET_SRC (set))) |
---|
1015 | optimize_reg_copy_2 (insn, dest, SET_SRC (set)); |
---|
1016 | |
---|
1017 | /* Otherwise, we only handle the case of a pseudo register being set |
---|
1018 | once. */ |
---|
1019 | if (GET_CODE (dest) != REG |
---|
1020 | || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER |
---|
1021 | || reg_n_sets[regno] != 1) |
---|
1022 | continue; |
---|
1023 | |
---|
1024 | note = find_reg_note (insn, REG_EQUAL, NULL_RTX); |
---|
1025 | |
---|
1026 | /* Record this insn as initializing this register. */ |
---|
1027 | reg_equiv_init_insn[regno] = insn; |
---|
1028 | |
---|
1029 | /* If this register is known to be equal to a constant, record that |
---|
1030 | it is always equivalent to the constant. */ |
---|
1031 | if (note && CONSTANT_P (XEXP (note, 0))) |
---|
1032 | PUT_MODE (note, (enum machine_mode) REG_EQUIV); |
---|
1033 | |
---|
1034 | /* If this insn introduces a "constant" register, decrease the priority |
---|
1035 | of that register. Record this insn if the register is only used once |
---|
1036 | more and the equivalence value is the same as our source. |
---|
1037 | |
---|
1038 | The latter condition is checked for two reasons: First, it is an |
---|
1039 | indication that it may be more efficient to actually emit the insn |
---|
1040 | as written (if no registers are available, reload will substitute |
---|
1041 | the equivalence). Secondly, it avoids problems with any registers |
---|
1042 | dying in this insn whose death notes would be missed. |
---|
1043 | |
---|
1044 | If we don't have a REG_EQUIV note, see if this insn is loading |
---|
1045 | a register used only in one basic block from a MEM. If so, and the |
---|
1046 | MEM remains unchanged for the life of the register, add a REG_EQUIV |
---|
1047 | note. */ |
---|
1048 | |
---|
1049 | note = find_reg_note (insn, REG_EQUIV, NULL_RTX); |
---|
1050 | |
---|
1051 | if (note == 0 && reg_basic_block[regno] >= 0 |
---|
1052 | && GET_CODE (SET_SRC (set)) == MEM |
---|
1053 | && validate_equiv_mem (insn, dest, SET_SRC (set))) |
---|
1054 | REG_NOTES (insn) = note = gen_rtx (EXPR_LIST, REG_EQUIV, SET_SRC (set), |
---|
1055 | REG_NOTES (insn)); |
---|
1056 | |
---|
1057 | /* Don't mess with things live during setjmp. */ |
---|
1058 | if (note && reg_live_length[regno] >= 0) |
---|
1059 | { |
---|
1060 | int regno = REGNO (dest); |
---|
1061 | |
---|
1062 | /* Note that the statement below does not affect the priority |
---|
1063 | in local-alloc! */ |
---|
1064 | reg_live_length[regno] *= 2; |
---|
1065 | |
---|
1066 | /* If the register is referenced exactly twice, meaning it is set |
---|
1067 | once and used once, indicate that the reference may be replaced |
---|
1068 | by the equivalence we computed above. If the register is only |
---|
1069 | used in one basic block, this can't succeed or combine would |
---|
1070 | have done it. |
---|
1071 | |
---|
1072 | It would be nice to use "loop_depth * 2" in the compare |
---|
1073 | below. Unfortunately, LOOP_DEPTH need not be constant within |
---|
1074 | a basic block so this would be too complicated. |
---|
1075 | |
---|
1076 | This case normally occurs when a parameter is read from memory |
---|
1077 | and then used exactly once, not in a loop. */ |
---|
1078 | |
---|
1079 | if (reg_n_refs[regno] == 2 |
---|
1080 | && reg_basic_block[regno] < 0 |
---|
1081 | && rtx_equal_p (XEXP (note, 0), SET_SRC (set))) |
---|
1082 | reg_equiv_replacement[regno] = SET_SRC (set); |
---|
1083 | } |
---|
1084 | } |
---|
1085 | |
---|
1086 | /* Now scan all regs killed in an insn to see if any of them are registers |
---|
1087 | only used that once. If so, see if we can replace the reference with |
---|
1088 | the equivalent from. If we can, delete the initializing reference |
---|
1089 | and this register will go away. */ |
---|
1090 | for (insn = next_active_insn (get_insns ()); |
---|
1091 | insn; |
---|
1092 | insn = next_active_insn (insn)) |
---|
1093 | { |
---|
1094 | rtx link; |
---|
1095 | |
---|
1096 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) |
---|
1097 | if (REG_NOTE_KIND (link) == REG_DEAD |
---|
1098 | /* Make sure this insn still refers to the register. */ |
---|
1099 | && reg_mentioned_p (XEXP (link, 0), PATTERN (insn))) |
---|
1100 | { |
---|
1101 | int regno = REGNO (XEXP (link, 0)); |
---|
1102 | |
---|
1103 | if (reg_equiv_replacement[regno] |
---|
1104 | && validate_replace_rtx (regno_reg_rtx[regno], |
---|
1105 | reg_equiv_replacement[regno], insn)) |
---|
1106 | { |
---|
1107 | rtx equiv_insn = reg_equiv_init_insn[regno]; |
---|
1108 | |
---|
1109 | remove_death (regno, insn); |
---|
1110 | reg_n_refs[regno] = 0; |
---|
1111 | PUT_CODE (equiv_insn, NOTE); |
---|
1112 | NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED; |
---|
1113 | NOTE_SOURCE_FILE (equiv_insn) = 0; |
---|
1114 | } |
---|
1115 | } |
---|
1116 | } |
---|
1117 | } |
---|
1118 | |
---|
1119 | /* Allocate hard regs to the pseudo regs used only within block number B. |
---|
1120 | Only the pseudos that die but once can be handled. */ |
---|
1121 | |
---|
1122 | static void |
---|
1123 | block_alloc (b) |
---|
1124 | int b; |
---|
1125 | { |
---|
1126 | register int i, q; |
---|
1127 | register rtx insn; |
---|
1128 | rtx note; |
---|
1129 | int insn_number = 0; |
---|
1130 | int insn_count = 0; |
---|
1131 | int max_uid = get_max_uid (); |
---|
1132 | int *qty_order; |
---|
1133 | int no_conflict_combined_regno = -1; |
---|
1134 | /* Counter to prevent allocating more SCRATCHes than can be stored |
---|
1135 | in SCRATCH_LIST. */ |
---|
1136 | int scratches_allocated = scratch_index; |
---|
1137 | |
---|
1138 | /* Count the instructions in the basic block. */ |
---|
1139 | |
---|
1140 | insn = basic_block_end[b]; |
---|
1141 | while (1) |
---|
1142 | { |
---|
1143 | if (GET_CODE (insn) != NOTE) |
---|
1144 | if (++insn_count > max_uid) |
---|
1145 | abort (); |
---|
1146 | if (insn == basic_block_head[b]) |
---|
1147 | break; |
---|
1148 | insn = PREV_INSN (insn); |
---|
1149 | } |
---|
1150 | |
---|
1151 | /* +2 to leave room for a post_mark_life at the last insn and for |
---|
1152 | the birth of a CLOBBER in the first insn. */ |
---|
1153 | regs_live_at = (HARD_REG_SET *) alloca ((2 * insn_count + 2) |
---|
1154 | * sizeof (HARD_REG_SET)); |
---|
1155 | bzero ((char *) regs_live_at, (2 * insn_count + 2) * sizeof (HARD_REG_SET)); |
---|
1156 | |
---|
1157 | /* Initialize table of hardware registers currently live. */ |
---|
1158 | |
---|
1159 | #ifdef HARD_REG_SET |
---|
1160 | regs_live = *basic_block_live_at_start[b]; |
---|
1161 | #else |
---|
1162 | COPY_HARD_REG_SET (regs_live, basic_block_live_at_start[b]); |
---|
1163 | #endif |
---|
1164 | |
---|
1165 | /* This loop scans the instructions of the basic block |
---|
1166 | and assigns quantities to registers. |
---|
1167 | It computes which registers to tie. */ |
---|
1168 | |
---|
1169 | insn = basic_block_head[b]; |
---|
1170 | while (1) |
---|
1171 | { |
---|
1172 | register rtx body = PATTERN (insn); |
---|
1173 | |
---|
1174 | if (GET_CODE (insn) != NOTE) |
---|
1175 | insn_number++; |
---|
1176 | |
---|
1177 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') |
---|
1178 | { |
---|
1179 | register rtx link, set; |
---|
1180 | register int win = 0; |
---|
1181 | register rtx r0, r1; |
---|
1182 | int combined_regno = -1; |
---|
1183 | int i; |
---|
1184 | int insn_code_number = recog_memoized (insn); |
---|
1185 | |
---|
1186 | this_insn_number = insn_number; |
---|
1187 | this_insn = insn; |
---|
1188 | |
---|
1189 | if (insn_code_number >= 0) |
---|
1190 | insn_extract (insn); |
---|
1191 | which_alternative = -1; |
---|
1192 | |
---|
1193 | /* Is this insn suitable for tying two registers? |
---|
1194 | If so, try doing that. |
---|
1195 | Suitable insns are those with at least two operands and where |
---|
1196 | operand 0 is an output that is a register that is not |
---|
1197 | earlyclobber. |
---|
1198 | |
---|
1199 | We can tie operand 0 with some operand that dies in this insn. |
---|
1200 | First look for operands that are required to be in the same |
---|
1201 | register as operand 0. If we find such, only try tying that |
---|
1202 | operand or one that can be put into that operand if the |
---|
1203 | operation is commutative. If we don't find an operand |
---|
1204 | that is required to be in the same register as operand 0, |
---|
1205 | we can tie with any operand. |
---|
1206 | |
---|
1207 | Subregs in place of regs are also ok. |
---|
1208 | |
---|
1209 | If tying is done, WIN is set nonzero. */ |
---|
1210 | |
---|
1211 | if (insn_code_number >= 0 |
---|
1212 | #ifdef REGISTER_CONSTRAINTS |
---|
1213 | && insn_n_operands[insn_code_number] > 1 |
---|
1214 | && insn_operand_constraint[insn_code_number][0][0] == '=' |
---|
1215 | && insn_operand_constraint[insn_code_number][0][1] != '&' |
---|
1216 | #else |
---|
1217 | && GET_CODE (PATTERN (insn)) == SET |
---|
1218 | && rtx_equal_p (SET_DEST (PATTERN (insn)), recog_operand[0]) |
---|
1219 | #endif |
---|
1220 | ) |
---|
1221 | { |
---|
1222 | #ifdef REGISTER_CONSTRAINTS |
---|
1223 | /* If non-negative, is an operand that must match operand 0. */ |
---|
1224 | int must_match_0 = -1; |
---|
1225 | /* Counts number of alternatives that require a match with |
---|
1226 | operand 0. */ |
---|
1227 | int n_matching_alts = 0; |
---|
1228 | |
---|
1229 | for (i = 1; i < insn_n_operands[insn_code_number]; i++) |
---|
1230 | { |
---|
1231 | char *p = insn_operand_constraint[insn_code_number][i]; |
---|
1232 | int this_match = (requires_inout (p)); |
---|
1233 | |
---|
1234 | n_matching_alts += this_match; |
---|
1235 | if (this_match == insn_n_alternatives[insn_code_number]) |
---|
1236 | must_match_0 = i; |
---|
1237 | } |
---|
1238 | #endif |
---|
1239 | |
---|
1240 | r0 = recog_operand[0]; |
---|
1241 | for (i = 1; i < insn_n_operands[insn_code_number]; i++) |
---|
1242 | { |
---|
1243 | #ifdef REGISTER_CONSTRAINTS |
---|
1244 | /* Skip this operand if we found an operand that |
---|
1245 | must match operand 0 and this operand isn't it |
---|
1246 | and can't be made to be it by commutativity. */ |
---|
1247 | |
---|
1248 | if (must_match_0 >= 0 && i != must_match_0 |
---|
1249 | && ! (i == must_match_0 + 1 |
---|
1250 | && insn_operand_constraint[insn_code_number][i-1][0] == '%') |
---|
1251 | && ! (i == must_match_0 - 1 |
---|
1252 | && insn_operand_constraint[insn_code_number][i][0] == '%')) |
---|
1253 | continue; |
---|
1254 | |
---|
1255 | /* Likewise if each alternative has some operand that |
---|
1256 | must match operand zero. In that case, skip any |
---|
1257 | operand that doesn't list operand 0 since we know that |
---|
1258 | the operand always conflicts with operand 0. We |
---|
1259 | ignore commutatity in this case to keep things simple. */ |
---|
1260 | if (n_matching_alts == insn_n_alternatives[insn_code_number] |
---|
1261 | && (0 == requires_inout |
---|
1262 | (insn_operand_constraint[insn_code_number][i]))) |
---|
1263 | continue; |
---|
1264 | #endif |
---|
1265 | |
---|
1266 | r1 = recog_operand[i]; |
---|
1267 | |
---|
1268 | /* If the operand is an address, find a register in it. |
---|
1269 | There may be more than one register, but we only try one |
---|
1270 | of them. */ |
---|
1271 | if ( |
---|
1272 | #ifdef REGISTER_CONSTRAINTS |
---|
1273 | insn_operand_constraint[insn_code_number][i][0] == 'p' |
---|
1274 | #else |
---|
1275 | insn_operand_address_p[insn_code_number][i] |
---|
1276 | #endif |
---|
1277 | ) |
---|
1278 | while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT) |
---|
1279 | r1 = XEXP (r1, 0); |
---|
1280 | |
---|
1281 | if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG) |
---|
1282 | { |
---|
1283 | /* We have two priorities for hard register preferences. |
---|
1284 | If we have a move insn or an insn whose first input |
---|
1285 | can only be in the same register as the output, give |
---|
1286 | priority to an equivalence found from that insn. */ |
---|
1287 | int may_save_copy |
---|
1288 | = ((SET_DEST (body) == r0 && SET_SRC (body) == r1) |
---|
1289 | #ifdef REGISTER_CONSTRAINTS |
---|
1290 | || (r1 == recog_operand[i] && must_match_0 >= 0) |
---|
1291 | #endif |
---|
1292 | ); |
---|
1293 | |
---|
1294 | if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG) |
---|
1295 | win = combine_regs (r1, r0, may_save_copy, |
---|
1296 | insn_number, insn, 0); |
---|
1297 | } |
---|
1298 | if (win) |
---|
1299 | break; |
---|
1300 | } |
---|
1301 | } |
---|
1302 | |
---|
1303 | /* Recognize an insn sequence with an ultimate result |
---|
1304 | which can safely overlap one of the inputs. |
---|
1305 | The sequence begins with a CLOBBER of its result, |
---|
1306 | and ends with an insn that copies the result to itself |
---|
1307 | and has a REG_EQUAL note for an equivalent formula. |
---|
1308 | That note indicates what the inputs are. |
---|
1309 | The result and the input can overlap if each insn in |
---|
1310 | the sequence either doesn't mention the input |
---|
1311 | or has a REG_NO_CONFLICT note to inhibit the conflict. |
---|
1312 | |
---|
1313 | We do the combining test at the CLOBBER so that the |
---|
1314 | destination register won't have had a quantity number |
---|
1315 | assigned, since that would prevent combining. */ |
---|
1316 | |
---|
1317 | if (GET_CODE (PATTERN (insn)) == CLOBBER |
---|
1318 | && (r0 = XEXP (PATTERN (insn), 0), |
---|
1319 | GET_CODE (r0) == REG) |
---|
1320 | && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0 |
---|
1321 | && XEXP (link, 0) != 0 |
---|
1322 | && GET_CODE (XEXP (link, 0)) == INSN |
---|
1323 | && (set = single_set (XEXP (link, 0))) != 0 |
---|
1324 | && SET_DEST (set) == r0 && SET_SRC (set) == r0 |
---|
1325 | && (note = find_reg_note (XEXP (link, 0), REG_EQUAL, |
---|
1326 | NULL_RTX)) != 0) |
---|
1327 | { |
---|
1328 | if (r1 = XEXP (note, 0), GET_CODE (r1) == REG |
---|
1329 | /* Check that we have such a sequence. */ |
---|
1330 | && no_conflict_p (insn, r0, r1)) |
---|
1331 | win = combine_regs (r1, r0, 1, insn_number, insn, 1); |
---|
1332 | else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e' |
---|
1333 | && (r1 = XEXP (XEXP (note, 0), 0), |
---|
1334 | GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG) |
---|
1335 | && no_conflict_p (insn, r0, r1)) |
---|
1336 | win = combine_regs (r1, r0, 0, insn_number, insn, 1); |
---|
1337 | |
---|
1338 | /* Here we care if the operation to be computed is |
---|
1339 | commutative. */ |
---|
1340 | else if ((GET_CODE (XEXP (note, 0)) == EQ |
---|
1341 | || GET_CODE (XEXP (note, 0)) == NE |
---|
1342 | || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c') |
---|
1343 | && (r1 = XEXP (XEXP (note, 0), 1), |
---|
1344 | (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)) |
---|
1345 | && no_conflict_p (insn, r0, r1)) |
---|
1346 | win = combine_regs (r1, r0, 0, insn_number, insn, 1); |
---|
1347 | |
---|
1348 | /* If we did combine something, show the register number |
---|
1349 | in question so that we know to ignore its death. */ |
---|
1350 | if (win) |
---|
1351 | no_conflict_combined_regno = REGNO (r1); |
---|
1352 | } |
---|
1353 | |
---|
1354 | /* If registers were just tied, set COMBINED_REGNO |
---|
1355 | to the number of the register used in this insn |
---|
1356 | that was tied to the register set in this insn. |
---|
1357 | This register's qty should not be "killed". */ |
---|
1358 | |
---|
1359 | if (win) |
---|
1360 | { |
---|
1361 | while (GET_CODE (r1) == SUBREG) |
---|
1362 | r1 = SUBREG_REG (r1); |
---|
1363 | combined_regno = REGNO (r1); |
---|
1364 | } |
---|
1365 | |
---|
1366 | /* Mark the death of everything that dies in this instruction, |
---|
1367 | except for anything that was just combined. */ |
---|
1368 | |
---|
1369 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) |
---|
1370 | if (REG_NOTE_KIND (link) == REG_DEAD |
---|
1371 | && GET_CODE (XEXP (link, 0)) == REG |
---|
1372 | && combined_regno != REGNO (XEXP (link, 0)) |
---|
1373 | && (no_conflict_combined_regno != REGNO (XEXP (link, 0)) |
---|
1374 | || ! find_reg_note (insn, REG_NO_CONFLICT, XEXP (link, 0)))) |
---|
1375 | wipe_dead_reg (XEXP (link, 0), 0); |
---|
1376 | |
---|
1377 | /* Allocate qty numbers for all registers local to this block |
---|
1378 | that are born (set) in this instruction. |
---|
1379 | A pseudo that already has a qty is not changed. */ |
---|
1380 | |
---|
1381 | note_stores (PATTERN (insn), reg_is_set); |
---|
1382 | |
---|
1383 | /* If anything is set in this insn and then unused, mark it as dying |
---|
1384 | after this insn, so it will conflict with our outputs. This |
---|
1385 | can't match with something that combined, and it doesn't matter |
---|
1386 | if it did. Do this after the calls to reg_is_set since these |
---|
1387 | die after, not during, the current insn. */ |
---|
1388 | |
---|
1389 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) |
---|
1390 | if (REG_NOTE_KIND (link) == REG_UNUSED |
---|
1391 | && GET_CODE (XEXP (link, 0)) == REG) |
---|
1392 | wipe_dead_reg (XEXP (link, 0), 1); |
---|
1393 | |
---|
1394 | /* Allocate quantities for any SCRATCH operands of this insn. */ |
---|
1395 | |
---|
1396 | if (insn_code_number >= 0) |
---|
1397 | for (i = 0; i < insn_n_operands[insn_code_number]; i++) |
---|
1398 | if (GET_CODE (recog_operand[i]) == SCRATCH |
---|
1399 | && scratches_allocated++ < scratch_list_length) |
---|
1400 | alloc_qty_for_scratch (recog_operand[i], i, insn, |
---|
1401 | insn_code_number, insn_number); |
---|
1402 | |
---|
1403 | /* If this is an insn that has a REG_RETVAL note pointing at a |
---|
1404 | CLOBBER insn, we have reached the end of a REG_NO_CONFLICT |
---|
1405 | block, so clear any register number that combined within it. */ |
---|
1406 | if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0 |
---|
1407 | && GET_CODE (XEXP (note, 0)) == INSN |
---|
1408 | && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER) |
---|
1409 | no_conflict_combined_regno = -1; |
---|
1410 | } |
---|
1411 | |
---|
1412 | /* Set the registers live after INSN_NUMBER. Note that we never |
---|
1413 | record the registers live before the block's first insn, since no |
---|
1414 | pseudos we care about are live before that insn. */ |
---|
1415 | |
---|
1416 | IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live); |
---|
1417 | IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live); |
---|
1418 | |
---|
1419 | if (insn == basic_block_end[b]) |
---|
1420 | break; |
---|
1421 | |
---|
1422 | insn = NEXT_INSN (insn); |
---|
1423 | } |
---|
1424 | |
---|
1425 | /* Now every register that is local to this basic block |
---|
1426 | should have been given a quantity, or else -1 meaning ignore it. |
---|
1427 | Every quantity should have a known birth and death. |
---|
1428 | |
---|
1429 | Order the qtys so we assign them registers in order of the |
---|
1430 | number of suggested registers they need so we allocate those with |
---|
1431 | the most restrictive needs first. */ |
---|
1432 | |
---|
1433 | qty_order = (int *) alloca (next_qty * sizeof (int)); |
---|
1434 | for (i = 0; i < next_qty; i++) |
---|
1435 | qty_order[i] = i; |
---|
1436 | |
---|
1437 | #define EXCHANGE(I1, I2) \ |
---|
1438 | { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; } |
---|
1439 | |
---|
1440 | switch (next_qty) |
---|
1441 | { |
---|
1442 | case 3: |
---|
1443 | /* Make qty_order[2] be the one to allocate last. */ |
---|
1444 | if (qty_sugg_compare (0, 1) > 0) |
---|
1445 | EXCHANGE (0, 1); |
---|
1446 | if (qty_sugg_compare (1, 2) > 0) |
---|
1447 | EXCHANGE (2, 1); |
---|
1448 | |
---|
1449 | /* ... Fall through ... */ |
---|
1450 | case 2: |
---|
1451 | /* Put the best one to allocate in qty_order[0]. */ |
---|
1452 | if (qty_sugg_compare (0, 1) > 0) |
---|
1453 | EXCHANGE (0, 1); |
---|
1454 | |
---|
1455 | /* ... Fall through ... */ |
---|
1456 | |
---|
1457 | case 1: |
---|
1458 | case 0: |
---|
1459 | /* Nothing to do here. */ |
---|
1460 | break; |
---|
1461 | |
---|
1462 | default: |
---|
1463 | qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1); |
---|
1464 | } |
---|
1465 | |
---|
1466 | /* Try to put each quantity in a suggested physical register, if it has one. |
---|
1467 | This may cause registers to be allocated that otherwise wouldn't be, but |
---|
1468 | this seems acceptable in local allocation (unlike global allocation). */ |
---|
1469 | for (i = 0; i < next_qty; i++) |
---|
1470 | { |
---|
1471 | q = qty_order[i]; |
---|
1472 | if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0) |
---|
1473 | qty_phys_reg[q] = find_free_reg (qty_min_class[q], qty_mode[q], q, |
---|
1474 | 0, 1, qty_birth[q], qty_death[q]); |
---|
1475 | else |
---|
1476 | qty_phys_reg[q] = -1; |
---|
1477 | } |
---|
1478 | |
---|
1479 | /* Order the qtys so we assign them registers in order of |
---|
1480 | decreasing length of life. Normally call qsort, but if we |
---|
1481 | have only a very small number of quantities, sort them ourselves. */ |
---|
1482 | |
---|
1483 | for (i = 0; i < next_qty; i++) |
---|
1484 | qty_order[i] = i; |
---|
1485 | |
---|
1486 | #define EXCHANGE(I1, I2) \ |
---|
1487 | { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; } |
---|
1488 | |
---|
1489 | switch (next_qty) |
---|
1490 | { |
---|
1491 | case 3: |
---|
1492 | /* Make qty_order[2] be the one to allocate last. */ |
---|
1493 | if (qty_compare (0, 1) > 0) |
---|
1494 | EXCHANGE (0, 1); |
---|
1495 | if (qty_compare (1, 2) > 0) |
---|
1496 | EXCHANGE (2, 1); |
---|
1497 | |
---|
1498 | /* ... Fall through ... */ |
---|
1499 | case 2: |
---|
1500 | /* Put the best one to allocate in qty_order[0]. */ |
---|
1501 | if (qty_compare (0, 1) > 0) |
---|
1502 | EXCHANGE (0, 1); |
---|
1503 | |
---|
1504 | /* ... Fall through ... */ |
---|
1505 | |
---|
1506 | case 1: |
---|
1507 | case 0: |
---|
1508 | /* Nothing to do here. */ |
---|
1509 | break; |
---|
1510 | |
---|
1511 | default: |
---|
1512 | qsort (qty_order, next_qty, sizeof (int), qty_compare_1); |
---|
1513 | } |
---|
1514 | |
---|
1515 | /* Now for each qty that is not a hardware register, |
---|
1516 | look for a hardware register to put it in. |
---|
1517 | First try the register class that is cheapest for this qty, |
---|
1518 | if there is more than one class. */ |
---|
1519 | |
---|
1520 | for (i = 0; i < next_qty; i++) |
---|
1521 | { |
---|
1522 | q = qty_order[i]; |
---|
1523 | if (qty_phys_reg[q] < 0) |
---|
1524 | { |
---|
1525 | if (N_REG_CLASSES > 1) |
---|
1526 | { |
---|
1527 | qty_phys_reg[q] = find_free_reg (qty_min_class[q], |
---|
1528 | qty_mode[q], q, 0, 0, |
---|
1529 | qty_birth[q], qty_death[q]); |
---|
1530 | if (qty_phys_reg[q] >= 0) |
---|
1531 | continue; |
---|
1532 | } |
---|
1533 | |
---|
1534 | if (qty_alternate_class[q] != NO_REGS) |
---|
1535 | qty_phys_reg[q] = find_free_reg (qty_alternate_class[q], |
---|
1536 | qty_mode[q], q, 0, 0, |
---|
1537 | qty_birth[q], qty_death[q]); |
---|
1538 | } |
---|
1539 | } |
---|
1540 | |
---|
1541 | /* Now propagate the register assignments |
---|
1542 | to the pseudo regs belonging to the qtys. */ |
---|
1543 | |
---|
1544 | for (q = 0; q < next_qty; q++) |
---|
1545 | if (qty_phys_reg[q] >= 0) |
---|
1546 | { |
---|
1547 | for (i = qty_first_reg[q]; i >= 0; i = reg_next_in_qty[i]) |
---|
1548 | reg_renumber[i] = qty_phys_reg[q] + reg_offset[i]; |
---|
1549 | if (qty_scratch_rtx[q]) |
---|
1550 | { |
---|
1551 | if (GET_CODE (qty_scratch_rtx[q]) == REG) |
---|
1552 | abort (); |
---|
1553 | PUT_CODE (qty_scratch_rtx[q], REG); |
---|
1554 | REGNO (qty_scratch_rtx[q]) = qty_phys_reg[q]; |
---|
1555 | |
---|
1556 | scratch_block[scratch_index] = b; |
---|
1557 | scratch_list[scratch_index++] = qty_scratch_rtx[q]; |
---|
1558 | |
---|
1559 | /* Must clear the USED field, because it will have been set by |
---|
1560 | copy_rtx_if_shared, but the leaf_register code expects that |
---|
1561 | it is zero in all REG rtx. copy_rtx_if_shared does not set the |
---|
1562 | used bit for REGs, but does for SCRATCHes. */ |
---|
1563 | qty_scratch_rtx[q]->used = 0; |
---|
1564 | } |
---|
1565 | } |
---|
1566 | } |
---|
1567 | |
---|
1568 | /* Compare two quantities' priority for getting real registers. |
---|
1569 | We give shorter-lived quantities higher priority. |
---|
1570 | Quantities with more references are also preferred, as are quantities that |
---|
1571 | require multiple registers. This is the identical prioritization as |
---|
1572 | done by global-alloc. |
---|
1573 | |
---|
1574 | We used to give preference to registers with *longer* lives, but using |
---|
1575 | the same algorithm in both local- and global-alloc can speed up execution |
---|
1576 | of some programs by as much as a factor of three! */ |
---|
1577 | |
---|
1578 | static int |
---|
1579 | qty_compare (q1, q2) |
---|
1580 | int q1, q2; |
---|
1581 | { |
---|
1582 | /* Note that the quotient will never be bigger than |
---|
1583 | the value of floor_log2 times the maximum number of |
---|
1584 | times a register can occur in one insn (surely less than 100). |
---|
1585 | Multiplying this by 10000 can't overflow. */ |
---|
1586 | register int pri1 |
---|
1587 | = (((double) (floor_log2 (qty_n_refs[q1]) * qty_n_refs[q1] * qty_size[q1]) |
---|
1588 | / (qty_death[q1] - qty_birth[q1])) |
---|
1589 | * 10000); |
---|
1590 | register int pri2 |
---|
1591 | = (((double) (floor_log2 (qty_n_refs[q2]) * qty_n_refs[q2] * qty_size[q2]) |
---|
1592 | / (qty_death[q2] - qty_birth[q2])) |
---|
1593 | * 10000); |
---|
1594 | return pri2 - pri1; |
---|
1595 | } |
---|
1596 | |
---|
1597 | static int |
---|
1598 | qty_compare_1 (q1, q2) |
---|
1599 | int *q1, *q2; |
---|
1600 | { |
---|
1601 | register int tem; |
---|
1602 | |
---|
1603 | /* Note that the quotient will never be bigger than |
---|
1604 | the value of floor_log2 times the maximum number of |
---|
1605 | times a register can occur in one insn (surely less than 100). |
---|
1606 | Multiplying this by 10000 can't overflow. */ |
---|
1607 | register int pri1 |
---|
1608 | = (((double) (floor_log2 (qty_n_refs[*q1]) * qty_n_refs[*q1] |
---|
1609 | * qty_size[*q1]) |
---|
1610 | / (qty_death[*q1] - qty_birth[*q1])) |
---|
1611 | * 10000); |
---|
1612 | register int pri2 |
---|
1613 | = (((double) (floor_log2 (qty_n_refs[*q2]) * qty_n_refs[*q2] |
---|
1614 | * qty_size[*q2]) |
---|
1615 | / (qty_death[*q2] - qty_birth[*q2])) |
---|
1616 | * 10000); |
---|
1617 | |
---|
1618 | tem = pri2 - pri1; |
---|
1619 | if (tem != 0) return tem; |
---|
1620 | /* If qtys are equally good, sort by qty number, |
---|
1621 | so that the results of qsort leave nothing to chance. */ |
---|
1622 | return *q1 - *q2; |
---|
1623 | } |
---|
1624 | |
---|
1625 | /* Compare two quantities' priority for getting real registers. This version |
---|
1626 | is called for quantities that have suggested hard registers. First priority |
---|
1627 | goes to quantities that have copy preferences, then to those that have |
---|
1628 | normal preferences. Within those groups, quantities with the lower |
---|
1629 | number of preferences have the highest priority. Of those, we use the same |
---|
1630 | algorithm as above. */ |
---|
1631 | |
---|
1632 | static int |
---|
1633 | qty_sugg_compare (q1, q2) |
---|
1634 | int q1, q2; |
---|
1635 | { |
---|
1636 | register int sugg1 = (qty_phys_num_copy_sugg[q1] |
---|
1637 | ? qty_phys_num_copy_sugg[q1] |
---|
1638 | : qty_phys_num_sugg[q1] * FIRST_PSEUDO_REGISTER); |
---|
1639 | register int sugg2 = (qty_phys_num_copy_sugg[q2] |
---|
1640 | ? qty_phys_num_copy_sugg[q2] |
---|
1641 | : qty_phys_num_sugg[q2] * FIRST_PSEUDO_REGISTER); |
---|
1642 | /* Note that the quotient will never be bigger than |
---|
1643 | the value of floor_log2 times the maximum number of |
---|
1644 | times a register can occur in one insn (surely less than 100). |
---|
1645 | Multiplying this by 10000 can't overflow. */ |
---|
1646 | register int pri1 |
---|
1647 | = (((double) (floor_log2 (qty_n_refs[q1]) * qty_n_refs[q1] * qty_size[q1]) |
---|
1648 | / (qty_death[q1] - qty_birth[q1])) |
---|
1649 | * 10000); |
---|
1650 | register int pri2 |
---|
1651 | = (((double) (floor_log2 (qty_n_refs[q2]) * qty_n_refs[q2] * qty_size[q2]) |
---|
1652 | / (qty_death[q2] - qty_birth[q2])) |
---|
1653 | * 10000); |
---|
1654 | |
---|
1655 | if (sugg1 != sugg2) |
---|
1656 | return sugg1 - sugg2; |
---|
1657 | |
---|
1658 | return pri2 - pri1; |
---|
1659 | } |
---|
1660 | |
---|
1661 | static int |
---|
1662 | qty_sugg_compare_1 (q1, q2) |
---|
1663 | int *q1, *q2; |
---|
1664 | { |
---|
1665 | register int sugg1 = (qty_phys_num_copy_sugg[*q1] |
---|
1666 | ? qty_phys_num_copy_sugg[*q1] |
---|
1667 | : qty_phys_num_sugg[*q1] * FIRST_PSEUDO_REGISTER); |
---|
1668 | register int sugg2 = (qty_phys_num_copy_sugg[*q2] |
---|
1669 | ? qty_phys_num_copy_sugg[*q2] |
---|
1670 | : qty_phys_num_sugg[*q2] * FIRST_PSEUDO_REGISTER); |
---|
1671 | |
---|
1672 | /* Note that the quotient will never be bigger than |
---|
1673 | the value of floor_log2 times the maximum number of |
---|
1674 | times a register can occur in one insn (surely less than 100). |
---|
1675 | Multiplying this by 10000 can't overflow. */ |
---|
1676 | register int pri1 |
---|
1677 | = (((double) (floor_log2 (qty_n_refs[*q1]) * qty_n_refs[*q1] |
---|
1678 | * qty_size[*q1]) |
---|
1679 | / (qty_death[*q1] - qty_birth[*q1])) |
---|
1680 | * 10000); |
---|
1681 | register int pri2 |
---|
1682 | = (((double) (floor_log2 (qty_n_refs[*q2]) * qty_n_refs[*q2] |
---|
1683 | * qty_size[*q2]) |
---|
1684 | / (qty_death[*q2] - qty_birth[*q2])) |
---|
1685 | * 10000); |
---|
1686 | |
---|
1687 | if (sugg1 != sugg2) |
---|
1688 | return sugg1 - sugg2; |
---|
1689 | |
---|
1690 | if (pri1 != pri2) |
---|
1691 | return pri2 - pri1; |
---|
1692 | |
---|
1693 | /* If qtys are equally good, sort by qty number, |
---|
1694 | so that the results of qsort leave nothing to chance. */ |
---|
1695 | return *q1 - *q2; |
---|
1696 | } |
---|
1697 | |
---|
1698 | /* Attempt to combine the two registers (rtx's) USEDREG and SETREG. |
---|
1699 | Returns 1 if have done so, or 0 if cannot. |
---|
1700 | |
---|
1701 | Combining registers means marking them as having the same quantity |
---|
1702 | and adjusting the offsets within the quantity if either of |
---|
1703 | them is a SUBREG). |
---|
1704 | |
---|
1705 | We don't actually combine a hard reg with a pseudo; instead |
---|
1706 | we just record the hard reg as the suggestion for the pseudo's quantity. |
---|
1707 | If we really combined them, we could lose if the pseudo lives |
---|
1708 | across an insn that clobbers the hard reg (eg, movstr). |
---|
1709 | |
---|
1710 | ALREADY_DEAD is non-zero if USEDREG is known to be dead even though |
---|
1711 | there is no REG_DEAD note on INSN. This occurs during the processing |
---|
1712 | of REG_NO_CONFLICT blocks. |
---|
1713 | |
---|
1714 | MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to |
---|
1715 | SETREG or if the input and output must share a register. |
---|
1716 | In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG. |
---|
1717 | |
---|
1718 | There are elaborate checks for the validity of combining. */ |
---|
1719 | |
---|
1720 | |
---|
1721 | static int |
---|
1722 | combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead) |
---|
1723 | rtx usedreg, setreg; |
---|
1724 | int may_save_copy; |
---|
1725 | int insn_number; |
---|
1726 | rtx insn; |
---|
1727 | int already_dead; |
---|
1728 | { |
---|
1729 | register int ureg, sreg; |
---|
1730 | register int offset = 0; |
---|
1731 | int usize, ssize; |
---|
1732 | register int sqty; |
---|
1733 | |
---|
1734 | /* Determine the numbers and sizes of registers being used. If a subreg |
---|
1735 | is present that does not change the entire register, don't consider |
---|
1736 | this a copy insn. */ |
---|
1737 | |
---|
1738 | while (GET_CODE (usedreg) == SUBREG) |
---|
1739 | { |
---|
1740 | if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg))) > UNITS_PER_WORD) |
---|
1741 | may_save_copy = 0; |
---|
1742 | offset += SUBREG_WORD (usedreg); |
---|
1743 | usedreg = SUBREG_REG (usedreg); |
---|
1744 | } |
---|
1745 | if (GET_CODE (usedreg) != REG) |
---|
1746 | return 0; |
---|
1747 | ureg = REGNO (usedreg); |
---|
1748 | usize = REG_SIZE (usedreg); |
---|
1749 | |
---|
1750 | while (GET_CODE (setreg) == SUBREG) |
---|
1751 | { |
---|
1752 | if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg))) > UNITS_PER_WORD) |
---|
1753 | may_save_copy = 0; |
---|
1754 | offset -= SUBREG_WORD (setreg); |
---|
1755 | setreg = SUBREG_REG (setreg); |
---|
1756 | } |
---|
1757 | if (GET_CODE (setreg) != REG) |
---|
1758 | return 0; |
---|
1759 | sreg = REGNO (setreg); |
---|
1760 | ssize = REG_SIZE (setreg); |
---|
1761 | |
---|
1762 | /* If UREG is a pseudo-register that hasn't already been assigned a |
---|
1763 | quantity number, it means that it is not local to this block or dies |
---|
1764 | more than once. In either event, we can't do anything with it. */ |
---|
1765 | if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0) |
---|
1766 | /* Do not combine registers unless one fits within the other. */ |
---|
1767 | || (offset > 0 && usize + offset > ssize) |
---|
1768 | || (offset < 0 && usize + offset < ssize) |
---|
1769 | /* Do not combine with a smaller already-assigned object |
---|
1770 | if that smaller object is already combined with something bigger. */ |
---|
1771 | || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER |
---|
1772 | && usize < qty_size[reg_qty[ureg]]) |
---|
1773 | /* Can't combine if SREG is not a register we can allocate. */ |
---|
1774 | || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1) |
---|
1775 | /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note. |
---|
1776 | These have already been taken care of. This probably wouldn't |
---|
1777 | combine anyway, but don't take any chances. */ |
---|
1778 | || (ureg >= FIRST_PSEUDO_REGISTER |
---|
1779 | && find_reg_note (insn, REG_NO_CONFLICT, usedreg)) |
---|
1780 | /* Don't tie something to itself. In most cases it would make no |
---|
1781 | difference, but it would screw up if the reg being tied to itself |
---|
1782 | also dies in this insn. */ |
---|
1783 | || ureg == sreg |
---|
1784 | /* Don't try to connect two different hardware registers. */ |
---|
1785 | || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER) |
---|
1786 | /* Don't connect two different machine modes if they have different |
---|
1787 | implications as to which registers may be used. */ |
---|
1788 | || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg))) |
---|
1789 | return 0; |
---|
1790 | |
---|
1791 | /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in |
---|
1792 | qty_phys_sugg for the pseudo instead of tying them. |
---|
1793 | |
---|
1794 | Return "failure" so that the lifespan of UREG is terminated here; |
---|
1795 | that way the two lifespans will be disjoint and nothing will prevent |
---|
1796 | the pseudo reg from being given this hard reg. */ |
---|
1797 | |
---|
1798 | if (ureg < FIRST_PSEUDO_REGISTER) |
---|
1799 | { |
---|
1800 | /* Allocate a quantity number so we have a place to put our |
---|
1801 | suggestions. */ |
---|
1802 | if (reg_qty[sreg] == -2) |
---|
1803 | reg_is_born (setreg, 2 * insn_number); |
---|
1804 | |
---|
1805 | if (reg_qty[sreg] >= 0) |
---|
1806 | { |
---|
1807 | if (may_save_copy |
---|
1808 | && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg)) |
---|
1809 | { |
---|
1810 | SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg); |
---|
1811 | qty_phys_num_copy_sugg[reg_qty[sreg]]++; |
---|
1812 | } |
---|
1813 | else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg)) |
---|
1814 | { |
---|
1815 | SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg); |
---|
1816 | qty_phys_num_sugg[reg_qty[sreg]]++; |
---|
1817 | } |
---|
1818 | } |
---|
1819 | return 0; |
---|
1820 | } |
---|
1821 | |
---|
1822 | /* Similarly for SREG a hard register and UREG a pseudo register. */ |
---|
1823 | |
---|
1824 | if (sreg < FIRST_PSEUDO_REGISTER) |
---|
1825 | { |
---|
1826 | if (may_save_copy |
---|
1827 | && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg)) |
---|
1828 | { |
---|
1829 | SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg); |
---|
1830 | qty_phys_num_copy_sugg[reg_qty[ureg]]++; |
---|
1831 | } |
---|
1832 | else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg)) |
---|
1833 | { |
---|
1834 | SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg); |
---|
1835 | qty_phys_num_sugg[reg_qty[ureg]]++; |
---|
1836 | } |
---|
1837 | return 0; |
---|
1838 | } |
---|
1839 | |
---|
1840 | /* At this point we know that SREG and UREG are both pseudos. |
---|
1841 | Do nothing if SREG already has a quantity or is a register that we |
---|
1842 | don't allocate. */ |
---|
1843 | if (reg_qty[sreg] >= -1 |
---|
1844 | /* If we are not going to let any regs live across calls, |
---|
1845 | don't tie a call-crossing reg to a non-call-crossing reg. */ |
---|
1846 | || (current_function_has_nonlocal_label |
---|
1847 | && ((reg_n_calls_crossed[ureg] > 0) |
---|
1848 | != (reg_n_calls_crossed[sreg] > 0)))) |
---|
1849 | return 0; |
---|
1850 | |
---|
1851 | /* We don't already know about SREG, so tie it to UREG |
---|
1852 | if this is the last use of UREG, provided the classes they want |
---|
1853 | are compatible. */ |
---|
1854 | |
---|
1855 | if ((already_dead || find_regno_note (insn, REG_DEAD, ureg)) |
---|
1856 | && reg_meets_class_p (sreg, qty_min_class[reg_qty[ureg]])) |
---|
1857 | { |
---|
1858 | /* Add SREG to UREG's quantity. */ |
---|
1859 | sqty = reg_qty[ureg]; |
---|
1860 | reg_qty[sreg] = sqty; |
---|
1861 | reg_offset[sreg] = reg_offset[ureg] + offset; |
---|
1862 | reg_next_in_qty[sreg] = qty_first_reg[sqty]; |
---|
1863 | qty_first_reg[sqty] = sreg; |
---|
1864 | |
---|
1865 | /* If SREG's reg class is smaller, set qty_min_class[SQTY]. */ |
---|
1866 | update_qty_class (sqty, sreg); |
---|
1867 | |
---|
1868 | /* Update info about quantity SQTY. */ |
---|
1869 | qty_n_calls_crossed[sqty] += reg_n_calls_crossed[sreg]; |
---|
1870 | qty_n_refs[sqty] += reg_n_refs[sreg]; |
---|
1871 | if (usize < ssize) |
---|
1872 | { |
---|
1873 | register int i; |
---|
1874 | |
---|
1875 | for (i = qty_first_reg[sqty]; i >= 0; i = reg_next_in_qty[i]) |
---|
1876 | reg_offset[i] -= offset; |
---|
1877 | |
---|
1878 | qty_size[sqty] = ssize; |
---|
1879 | qty_mode[sqty] = GET_MODE (setreg); |
---|
1880 | } |
---|
1881 | } |
---|
1882 | else |
---|
1883 | return 0; |
---|
1884 | |
---|
1885 | return 1; |
---|
1886 | } |
---|
1887 | |
---|
1888 | /* Return 1 if the preferred class of REG allows it to be tied |
---|
1889 | to a quantity or register whose class is CLASS. |
---|
1890 | True if REG's reg class either contains or is contained in CLASS. */ |
---|
1891 | |
---|
1892 | static int |
---|
1893 | reg_meets_class_p (reg, class) |
---|
1894 | int reg; |
---|
1895 | enum reg_class class; |
---|
1896 | { |
---|
1897 | register enum reg_class rclass = reg_preferred_class (reg); |
---|
1898 | return (reg_class_subset_p (rclass, class) |
---|
1899 | || reg_class_subset_p (class, rclass)); |
---|
1900 | } |
---|
1901 | |
---|
1902 | /* Return 1 if the two specified classes have registers in common. |
---|
1903 | If CALL_SAVED, then consider only call-saved registers. */ |
---|
1904 | |
---|
1905 | static int |
---|
1906 | reg_classes_overlap_p (c1, c2, call_saved) |
---|
1907 | register enum reg_class c1; |
---|
1908 | register enum reg_class c2; |
---|
1909 | int call_saved; |
---|
1910 | { |
---|
1911 | HARD_REG_SET c; |
---|
1912 | int i; |
---|
1913 | |
---|
1914 | COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); |
---|
1915 | AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); |
---|
1916 | |
---|
1917 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
---|
1918 | if (TEST_HARD_REG_BIT (c, i) |
---|
1919 | && (! call_saved || ! call_used_regs[i])) |
---|
1920 | return 1; |
---|
1921 | |
---|
1922 | return 0; |
---|
1923 | } |
---|
1924 | |
---|
1925 | /* Update the class of QTY assuming that REG is being tied to it. */ |
---|
1926 | |
---|
1927 | static void |
---|
1928 | update_qty_class (qty, reg) |
---|
1929 | int qty; |
---|
1930 | int reg; |
---|
1931 | { |
---|
1932 | enum reg_class rclass = reg_preferred_class (reg); |
---|
1933 | if (reg_class_subset_p (rclass, qty_min_class[qty])) |
---|
1934 | qty_min_class[qty] = rclass; |
---|
1935 | |
---|
1936 | rclass = reg_alternate_class (reg); |
---|
1937 | if (reg_class_subset_p (rclass, qty_alternate_class[qty])) |
---|
1938 | qty_alternate_class[qty] = rclass; |
---|
1939 | |
---|
1940 | if (reg_changes_size[reg]) |
---|
1941 | qty_changes_size[qty] = 1; |
---|
1942 | } |
---|
1943 | |
---|
1944 | /* Handle something which alters the value of an rtx REG. |
---|
1945 | |
---|
1946 | REG is whatever is set or clobbered. SETTER is the rtx that |
---|
1947 | is modifying the register. |
---|
1948 | |
---|
1949 | If it is not really a register, we do nothing. |
---|
1950 | The file-global variables `this_insn' and `this_insn_number' |
---|
1951 | carry info from `block_alloc'. */ |
---|
1952 | |
---|
1953 | static void |
---|
1954 | reg_is_set (reg, setter) |
---|
1955 | rtx reg; |
---|
1956 | rtx setter; |
---|
1957 | { |
---|
1958 | /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of |
---|
1959 | a hard register. These may actually not exist any more. */ |
---|
1960 | |
---|
1961 | if (GET_CODE (reg) != SUBREG |
---|
1962 | && GET_CODE (reg) != REG) |
---|
1963 | return; |
---|
1964 | |
---|
1965 | /* Mark this register as being born. If it is used in a CLOBBER, mark |
---|
1966 | it as being born halfway between the previous insn and this insn so that |
---|
1967 | it conflicts with our inputs but not the outputs of the previous insn. */ |
---|
1968 | |
---|
1969 | reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER)); |
---|
1970 | } |
---|
1971 | |
---|
1972 | /* Handle beginning of the life of register REG. |
---|
1973 | BIRTH is the index at which this is happening. */ |
---|
1974 | |
---|
1975 | static void |
---|
1976 | reg_is_born (reg, birth) |
---|
1977 | rtx reg; |
---|
1978 | int birth; |
---|
1979 | { |
---|
1980 | register int regno; |
---|
1981 | |
---|
1982 | if (GET_CODE (reg) == SUBREG) |
---|
1983 | regno = REGNO (SUBREG_REG (reg)) + SUBREG_WORD (reg); |
---|
1984 | else |
---|
1985 | regno = REGNO (reg); |
---|
1986 | |
---|
1987 | if (regno < FIRST_PSEUDO_REGISTER) |
---|
1988 | { |
---|
1989 | mark_life (regno, GET_MODE (reg), 1); |
---|
1990 | |
---|
1991 | /* If the register was to have been born earlier that the present |
---|
1992 | insn, mark it as live where it is actually born. */ |
---|
1993 | if (birth < 2 * this_insn_number) |
---|
1994 | post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number); |
---|
1995 | } |
---|
1996 | else |
---|
1997 | { |
---|
1998 | if (reg_qty[regno] == -2) |
---|
1999 | alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth); |
---|
2000 | |
---|
2001 | /* If this register has a quantity number, show that it isn't dead. */ |
---|
2002 | if (reg_qty[regno] >= 0) |
---|
2003 | qty_death[reg_qty[regno]] = -1; |
---|
2004 | } |
---|
2005 | } |
---|
2006 | |
---|
2007 | /* Record the death of REG in the current insn. If OUTPUT_P is non-zero, |
---|
2008 | REG is an output that is dying (i.e., it is never used), otherwise it |
---|
2009 | is an input (the normal case). |
---|
2010 | If OUTPUT_P is 1, then we extend the life past the end of this insn. */ |
---|
2011 | |
---|
2012 | static void |
---|
2013 | wipe_dead_reg (reg, output_p) |
---|
2014 | register rtx reg; |
---|
2015 | int output_p; |
---|
2016 | { |
---|
2017 | register int regno = REGNO (reg); |
---|
2018 | |
---|
2019 | /* If this insn has multiple results, |
---|
2020 | and the dead reg is used in one of the results, |
---|
2021 | extend its life to after this insn, |
---|
2022 | so it won't get allocated together with any other result of this insn. */ |
---|
2023 | if (GET_CODE (PATTERN (this_insn)) == PARALLEL |
---|
2024 | && !single_set (this_insn)) |
---|
2025 | { |
---|
2026 | int i; |
---|
2027 | for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--) |
---|
2028 | { |
---|
2029 | rtx set = XVECEXP (PATTERN (this_insn), 0, i); |
---|
2030 | if (GET_CODE (set) == SET |
---|
2031 | && GET_CODE (SET_DEST (set)) != REG |
---|
2032 | && !rtx_equal_p (reg, SET_DEST (set)) |
---|
2033 | && reg_overlap_mentioned_p (reg, SET_DEST (set))) |
---|
2034 | output_p = 1; |
---|
2035 | } |
---|
2036 | } |
---|
2037 | |
---|
2038 | /* If this register is used in an auto-increment address, then extend its |
---|
2039 | life to after this insn, so that it won't get allocated together with |
---|
2040 | the result of this insn. */ |
---|
2041 | if (! output_p && find_regno_note (this_insn, REG_INC, regno)) |
---|
2042 | output_p = 1; |
---|
2043 | |
---|
2044 | if (regno < FIRST_PSEUDO_REGISTER) |
---|
2045 | { |
---|
2046 | mark_life (regno, GET_MODE (reg), 0); |
---|
2047 | |
---|
2048 | /* If a hard register is dying as an output, mark it as in use at |
---|
2049 | the beginning of this insn (the above statement would cause this |
---|
2050 | not to happen). */ |
---|
2051 | if (output_p) |
---|
2052 | post_mark_life (regno, GET_MODE (reg), 1, |
---|
2053 | 2 * this_insn_number, 2 * this_insn_number+ 1); |
---|
2054 | } |
---|
2055 | |
---|
2056 | else if (reg_qty[regno] >= 0) |
---|
2057 | qty_death[reg_qty[regno]] = 2 * this_insn_number + output_p; |
---|
2058 | } |
---|
2059 | |
---|
2060 | /* Find a block of SIZE words of hard regs in reg_class CLASS |
---|
2061 | that can hold something of machine-mode MODE |
---|
2062 | (but actually we test only the first of the block for holding MODE) |
---|
2063 | and still free between insn BORN_INDEX and insn DEAD_INDEX, |
---|
2064 | and return the number of the first of them. |
---|
2065 | Return -1 if such a block cannot be found. |
---|
2066 | If QTY crosses calls, insist on a register preserved by calls, |
---|
2067 | unless ACCEPT_CALL_CLOBBERED is nonzero. |
---|
2068 | |
---|
2069 | If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested |
---|
2070 | register is available. If not, return -1. */ |
---|
2071 | |
---|
2072 | static int |
---|
2073 | find_free_reg (class, mode, qty, accept_call_clobbered, just_try_suggested, |
---|
2074 | born_index, dead_index) |
---|
2075 | enum reg_class class; |
---|
2076 | enum machine_mode mode; |
---|
2077 | int qty; |
---|
2078 | int accept_call_clobbered; |
---|
2079 | int just_try_suggested; |
---|
2080 | int born_index, dead_index; |
---|
2081 | { |
---|
2082 | register int i, ins; |
---|
2083 | #ifdef HARD_REG_SET |
---|
2084 | register /* Declare it register if it's a scalar. */ |
---|
2085 | #endif |
---|
2086 | HARD_REG_SET used, first_used; |
---|
2087 | #ifdef ELIMINABLE_REGS |
---|
2088 | static struct {int from, to; } eliminables[] = ELIMINABLE_REGS; |
---|
2089 | #endif |
---|
2090 | |
---|
2091 | /* Validate our parameters. */ |
---|
2092 | if (born_index < 0 || born_index > dead_index) |
---|
2093 | abort (); |
---|
2094 | |
---|
2095 | /* Don't let a pseudo live in a reg across a function call |
---|
2096 | if we might get a nonlocal goto. */ |
---|
2097 | if (current_function_has_nonlocal_label |
---|
2098 | && qty_n_calls_crossed[qty] > 0) |
---|
2099 | return -1; |
---|
2100 | |
---|
2101 | if (accept_call_clobbered) |
---|
2102 | COPY_HARD_REG_SET (used, call_fixed_reg_set); |
---|
2103 | else if (qty_n_calls_crossed[qty] == 0) |
---|
2104 | COPY_HARD_REG_SET (used, fixed_reg_set); |
---|
2105 | else |
---|
2106 | COPY_HARD_REG_SET (used, call_used_reg_set); |
---|
2107 | |
---|
2108 | for (ins = born_index; ins < dead_index; ins++) |
---|
2109 | IOR_HARD_REG_SET (used, regs_live_at[ins]); |
---|
2110 | |
---|
2111 | IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]); |
---|
2112 | |
---|
2113 | /* Don't use the frame pointer reg in local-alloc even if |
---|
2114 | we may omit the frame pointer, because if we do that and then we |
---|
2115 | need a frame pointer, reload won't know how to move the pseudo |
---|
2116 | to another hard reg. It can move only regs made by global-alloc. |
---|
2117 | |
---|
2118 | This is true of any register that can be eliminated. */ |
---|
2119 | #ifdef ELIMINABLE_REGS |
---|
2120 | for (i = 0; i < sizeof eliminables / sizeof eliminables[0]; i++) |
---|
2121 | SET_HARD_REG_BIT (used, eliminables[i].from); |
---|
2122 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM |
---|
2123 | /* If FRAME_POINTER_REGNUM is not a real register, then protect the one |
---|
2124 | that it might be eliminated into. */ |
---|
2125 | SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM); |
---|
2126 | #endif |
---|
2127 | #else |
---|
2128 | SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM); |
---|
2129 | #endif |
---|
2130 | |
---|
2131 | #ifdef CLASS_CANNOT_CHANGE_SIZE |
---|
2132 | if (qty_changes_size[qty]) |
---|
2133 | IOR_HARD_REG_SET (used, |
---|
2134 | reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE]); |
---|
2135 | #endif |
---|
2136 | |
---|
2137 | /* Normally, the registers that can be used for the first register in |
---|
2138 | a multi-register quantity are the same as those that can be used for |
---|
2139 | subsequent registers. However, if just trying suggested registers, |
---|
2140 | restrict our consideration to them. If there are copy-suggested |
---|
2141 | register, try them. Otherwise, try the arithmetic-suggested |
---|
2142 | registers. */ |
---|
2143 | COPY_HARD_REG_SET (first_used, used); |
---|
2144 | |
---|
2145 | if (just_try_suggested) |
---|
2146 | { |
---|
2147 | if (qty_phys_num_copy_sugg[qty] != 0) |
---|
2148 | IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qty]); |
---|
2149 | else |
---|
2150 | IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qty]); |
---|
2151 | } |
---|
2152 | |
---|
2153 | /* If all registers are excluded, we can't do anything. */ |
---|
2154 | GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail); |
---|
2155 | |
---|
2156 | /* If at least one would be suitable, test each hard reg. */ |
---|
2157 | |
---|
2158 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
---|
2159 | { |
---|
2160 | #ifdef REG_ALLOC_ORDER |
---|
2161 | int regno = reg_alloc_order[i]; |
---|
2162 | #else |
---|
2163 | int regno = i; |
---|
2164 | #endif |
---|
2165 | if (! TEST_HARD_REG_BIT (first_used, regno) |
---|
2166 | && HARD_REGNO_MODE_OK (regno, mode)) |
---|
2167 | { |
---|
2168 | register int j; |
---|
2169 | register int size1 = HARD_REGNO_NREGS (regno, mode); |
---|
2170 | for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++); |
---|
2171 | if (j == size1) |
---|
2172 | { |
---|
2173 | /* Mark that this register is in use between its birth and death |
---|
2174 | insns. */ |
---|
2175 | post_mark_life (regno, mode, 1, born_index, dead_index); |
---|
2176 | return regno; |
---|
2177 | } |
---|
2178 | #ifndef REG_ALLOC_ORDER |
---|
2179 | i += j; /* Skip starting points we know will lose */ |
---|
2180 | #endif |
---|
2181 | } |
---|
2182 | } |
---|
2183 | |
---|
2184 | fail: |
---|
2185 | |
---|
2186 | /* If we are just trying suggested register, we have just tried copy- |
---|
2187 | suggested registers, and there are arithmetic-suggested registers, |
---|
2188 | try them. */ |
---|
2189 | |
---|
2190 | /* If it would be profitable to allocate a call-clobbered register |
---|
2191 | and save and restore it around calls, do that. */ |
---|
2192 | if (just_try_suggested && qty_phys_num_copy_sugg[qty] != 0 |
---|
2193 | && qty_phys_num_sugg[qty] != 0) |
---|
2194 | { |
---|
2195 | /* Don't try the copy-suggested regs again. */ |
---|
2196 | qty_phys_num_copy_sugg[qty] = 0; |
---|
2197 | return find_free_reg (class, mode, qty, accept_call_clobbered, 1, |
---|
2198 | born_index, dead_index); |
---|
2199 | } |
---|
2200 | |
---|
2201 | /* We need not check to see if the current function has nonlocal |
---|
2202 | labels because we don't put any pseudos that are live over calls in |
---|
2203 | registers in that case. */ |
---|
2204 | |
---|
2205 | if (! accept_call_clobbered |
---|
2206 | && flag_caller_saves |
---|
2207 | && ! just_try_suggested |
---|
2208 | && qty_n_calls_crossed[qty] != 0 |
---|
2209 | && CALLER_SAVE_PROFITABLE (qty_n_refs[qty], qty_n_calls_crossed[qty])) |
---|
2210 | { |
---|
2211 | i = find_free_reg (class, mode, qty, 1, 0, born_index, dead_index); |
---|
2212 | if (i >= 0) |
---|
2213 | caller_save_needed = 1; |
---|
2214 | return i; |
---|
2215 | } |
---|
2216 | return -1; |
---|
2217 | } |
---|
2218 | |
---|
2219 | /* Mark that REGNO with machine-mode MODE is live starting from the current |
---|
2220 | insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE |
---|
2221 | is zero). */ |
---|
2222 | |
---|
2223 | static void |
---|
2224 | mark_life (regno, mode, life) |
---|
2225 | register int regno; |
---|
2226 | enum machine_mode mode; |
---|
2227 | int life; |
---|
2228 | { |
---|
2229 | register int j = HARD_REGNO_NREGS (regno, mode); |
---|
2230 | if (life) |
---|
2231 | while (--j >= 0) |
---|
2232 | SET_HARD_REG_BIT (regs_live, regno + j); |
---|
2233 | else |
---|
2234 | while (--j >= 0) |
---|
2235 | CLEAR_HARD_REG_BIT (regs_live, regno + j); |
---|
2236 | } |
---|
2237 | |
---|
2238 | /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE |
---|
2239 | is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive) |
---|
2240 | to insn number DEATH (exclusive). */ |
---|
2241 | |
---|
2242 | static void |
---|
2243 | post_mark_life (regno, mode, life, birth, death) |
---|
2244 | int regno; |
---|
2245 | enum machine_mode mode; |
---|
2246 | int life, birth, death; |
---|
2247 | { |
---|
2248 | register int j = HARD_REGNO_NREGS (regno, mode); |
---|
2249 | #ifdef HARD_REG_SET |
---|
2250 | register /* Declare it register if it's a scalar. */ |
---|
2251 | #endif |
---|
2252 | HARD_REG_SET this_reg; |
---|
2253 | |
---|
2254 | CLEAR_HARD_REG_SET (this_reg); |
---|
2255 | while (--j >= 0) |
---|
2256 | SET_HARD_REG_BIT (this_reg, regno + j); |
---|
2257 | |
---|
2258 | if (life) |
---|
2259 | while (birth < death) |
---|
2260 | { |
---|
2261 | IOR_HARD_REG_SET (regs_live_at[birth], this_reg); |
---|
2262 | birth++; |
---|
2263 | } |
---|
2264 | else |
---|
2265 | while (birth < death) |
---|
2266 | { |
---|
2267 | AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg); |
---|
2268 | birth++; |
---|
2269 | } |
---|
2270 | } |
---|
2271 | |
---|
2272 | /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0 |
---|
2273 | is the register being clobbered, and R1 is a register being used in |
---|
2274 | the equivalent expression. |
---|
2275 | |
---|
2276 | If R1 dies in the block and has a REG_NO_CONFLICT note on every insn |
---|
2277 | in which it is used, return 1. |
---|
2278 | |
---|
2279 | Otherwise, return 0. */ |
---|
2280 | |
---|
2281 | static int |
---|
2282 | no_conflict_p (insn, r0, r1) |
---|
2283 | rtx insn, r0, r1; |
---|
2284 | { |
---|
2285 | int ok = 0; |
---|
2286 | rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX); |
---|
2287 | rtx p, last; |
---|
2288 | |
---|
2289 | /* If R1 is a hard register, return 0 since we handle this case |
---|
2290 | when we scan the insns that actually use it. */ |
---|
2291 | |
---|
2292 | if (note == 0 |
---|
2293 | || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER) |
---|
2294 | || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG |
---|
2295 | && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER)) |
---|
2296 | return 0; |
---|
2297 | |
---|
2298 | last = XEXP (note, 0); |
---|
2299 | |
---|
2300 | for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p)) |
---|
2301 | if (GET_RTX_CLASS (GET_CODE (p)) == 'i') |
---|
2302 | { |
---|
2303 | if (find_reg_note (p, REG_DEAD, r1)) |
---|
2304 | ok = 1; |
---|
2305 | |
---|
2306 | if (reg_mentioned_p (r1, PATTERN (p)) |
---|
2307 | && ! find_reg_note (p, REG_NO_CONFLICT, r1)) |
---|
2308 | return 0; |
---|
2309 | } |
---|
2310 | |
---|
2311 | return ok; |
---|
2312 | } |
---|
2313 | |
---|
2314 | #ifdef REGISTER_CONSTRAINTS |
---|
2315 | |
---|
2316 | /* Return the number of alternatives for which the constraint string P |
---|
2317 | indicates that the operand must be equal to operand 0 and that no register |
---|
2318 | is acceptable. */ |
---|
2319 | |
---|
2320 | static int |
---|
2321 | requires_inout (p) |
---|
2322 | char *p; |
---|
2323 | { |
---|
2324 | char c; |
---|
2325 | int found_zero = 0; |
---|
2326 | int reg_allowed = 0; |
---|
2327 | int num_matching_alts = 0; |
---|
2328 | |
---|
2329 | while (c = *p++) |
---|
2330 | switch (c) |
---|
2331 | { |
---|
2332 | case '=': case '+': case '?': |
---|
2333 | case '#': case '&': case '!': |
---|
2334 | case '*': case '%': |
---|
2335 | case '1': case '2': case '3': case '4': |
---|
2336 | case 'm': case '<': case '>': case 'V': case 'o': |
---|
2337 | case 'E': case 'F': case 'G': case 'H': |
---|
2338 | case 's': case 'i': case 'n': |
---|
2339 | case 'I': case 'J': case 'K': case 'L': |
---|
2340 | case 'M': case 'N': case 'O': case 'P': |
---|
2341 | #ifdef EXTRA_CONSTRAINT |
---|
2342 | case 'Q': case 'R': case 'S': case 'T': case 'U': |
---|
2343 | #endif |
---|
2344 | case 'X': |
---|
2345 | /* These don't say anything we care about. */ |
---|
2346 | break; |
---|
2347 | |
---|
2348 | case ',': |
---|
2349 | if (found_zero && ! reg_allowed) |
---|
2350 | num_matching_alts++; |
---|
2351 | |
---|
2352 | found_zero = reg_allowed = 0; |
---|
2353 | break; |
---|
2354 | |
---|
2355 | case '0': |
---|
2356 | found_zero = 1; |
---|
2357 | break; |
---|
2358 | |
---|
2359 | case 'p': |
---|
2360 | case 'g': case 'r': |
---|
2361 | default: |
---|
2362 | reg_allowed = 1; |
---|
2363 | break; |
---|
2364 | } |
---|
2365 | |
---|
2366 | if (found_zero && ! reg_allowed) |
---|
2367 | num_matching_alts++; |
---|
2368 | |
---|
2369 | return num_matching_alts; |
---|
2370 | } |
---|
2371 | #endif /* REGISTER_CONSTRAINTS */ |
---|
2372 | |
---|
2373 | void |
---|
2374 | dump_local_alloc (file) |
---|
2375 | FILE *file; |
---|
2376 | { |
---|
2377 | register int i; |
---|
2378 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) |
---|
2379 | if (reg_renumber[i] != -1) |
---|
2380 | fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]); |
---|
2381 | } |
---|