1 | /* Compute register class preferences for pseudo-registers. |
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2 | Copyright (C) 1987, 88, 91, 92, 93, 1994 Free Software Foundation, Inc. |
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3 | |
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4 | This file is part of GNU CC. |
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5 | |
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6 | GNU CC is free software; you can redistribute it and/or modify |
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7 | it under the terms of the GNU General Public License as published by |
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8 | the Free Software Foundation; either version 2, or (at your option) |
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9 | any later version. |
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10 | |
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11 | GNU CC is distributed in the hope that it will be useful, |
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12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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14 | GNU General Public License for more details. |
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15 | |
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16 | You should have received a copy of the GNU General Public License |
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17 | along with GNU CC; see the file COPYING. If not, write to |
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18 | the Free Software Foundation, 59 Temple Place - Suite 330, |
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19 | Boston, MA 02111-1307, USA. */ |
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20 | |
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21 | |
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22 | /* This file contains two passes of the compiler: reg_scan and reg_class. |
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23 | It also defines some tables of information about the hardware registers |
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24 | and a function init_reg_sets to initialize the tables. */ |
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25 | |
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26 | #include "config.h" |
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27 | #include "rtl.h" |
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28 | #include "hard-reg-set.h" |
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29 | #include "flags.h" |
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30 | #include "basic-block.h" |
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31 | #include "regs.h" |
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32 | #include "insn-config.h" |
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33 | #include "recog.h" |
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34 | #include "reload.h" |
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35 | #include "real.h" |
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36 | #include "bytecode.h" |
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37 | |
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38 | #ifndef REGISTER_MOVE_COST |
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39 | #define REGISTER_MOVE_COST(x, y) 2 |
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40 | #endif |
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41 | |
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42 | #ifndef MEMORY_MOVE_COST |
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43 | #define MEMORY_MOVE_COST(x) 4 |
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44 | #endif |
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45 | |
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46 | /* If we have auto-increment or auto-decrement and we can have secondary |
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47 | reloads, we are not allowed to use classes requiring secondary |
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48 | reloads for pseudos auto-incremented since reload can't handle it. */ |
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49 | |
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50 | #ifdef AUTO_INC_DEC |
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51 | #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS) |
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52 | #define FORBIDDEN_INC_DEC_CLASSES |
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53 | #endif |
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54 | #endif |
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55 | |
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56 | /* Register tables used by many passes. */ |
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57 | |
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58 | /* Indexed by hard register number, contains 1 for registers |
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59 | that are fixed use (stack pointer, pc, frame pointer, etc.). |
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60 | These are the registers that cannot be used to allocate |
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61 | a pseudo reg whose life does not cross calls. */ |
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62 | |
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63 | char fixed_regs[FIRST_PSEUDO_REGISTER]; |
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64 | |
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65 | /* Same info as a HARD_REG_SET. */ |
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66 | |
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67 | HARD_REG_SET fixed_reg_set; |
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68 | |
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69 | /* Data for initializing the above. */ |
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70 | |
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71 | static char initial_fixed_regs[] = FIXED_REGISTERS; |
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72 | |
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73 | /* Indexed by hard register number, contains 1 for registers |
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74 | that are fixed use or are clobbered by function calls. |
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75 | These are the registers that cannot be used to allocate |
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76 | a pseudo reg whose life crosses calls. */ |
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77 | |
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78 | char call_used_regs[FIRST_PSEUDO_REGISTER]; |
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79 | |
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80 | /* Same info as a HARD_REG_SET. */ |
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81 | |
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82 | HARD_REG_SET call_used_reg_set; |
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83 | |
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84 | /* Data for initializing the above. */ |
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85 | |
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86 | static char initial_call_used_regs[] = CALL_USED_REGISTERS; |
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87 | |
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88 | /* Indexed by hard register number, contains 1 for registers that are |
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89 | fixed use -- i.e. in fixed_regs -- or a function value return register |
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90 | or STRUCT_VALUE_REGNUM or STATIC_CHAIN_REGNUM. These are the |
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91 | registers that cannot hold quantities across calls even if we are |
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92 | willing to save and restore them. */ |
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93 | |
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94 | char call_fixed_regs[FIRST_PSEUDO_REGISTER]; |
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95 | |
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96 | /* The same info as a HARD_REG_SET. */ |
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97 | |
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98 | HARD_REG_SET call_fixed_reg_set; |
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99 | |
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100 | /* Number of non-fixed registers. */ |
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101 | |
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102 | int n_non_fixed_regs; |
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103 | |
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104 | /* Indexed by hard register number, contains 1 for registers |
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105 | that are being used for global register decls. |
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106 | These must be exempt from ordinary flow analysis |
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107 | and are also considered fixed. */ |
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108 | |
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109 | char global_regs[FIRST_PSEUDO_REGISTER]; |
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110 | |
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111 | /* Table of register numbers in the order in which to try to use them. */ |
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112 | #ifdef REG_ALLOC_ORDER |
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113 | int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; |
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114 | #endif |
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115 | |
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116 | /* For each reg class, a HARD_REG_SET saying which registers are in it. */ |
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117 | |
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118 | HARD_REG_SET reg_class_contents[N_REG_CLASSES]; |
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119 | |
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120 | /* The same information, but as an array of unsigned ints. We copy from |
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121 | these unsigned ints to the table above. We do this so the tm.h files |
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122 | do not have to be aware of the wordsize for machines with <= 64 regs. */ |
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123 | |
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124 | #define N_REG_INTS \ |
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125 | ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT) |
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126 | |
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127 | static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS] |
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128 | = REG_CLASS_CONTENTS; |
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129 | |
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130 | /* For each reg class, number of regs it contains. */ |
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131 | |
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132 | int reg_class_size[N_REG_CLASSES]; |
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133 | |
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134 | /* For each reg class, table listing all the containing classes. */ |
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135 | |
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136 | enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; |
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137 | |
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138 | /* For each reg class, table listing all the classes contained in it. */ |
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139 | |
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140 | enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; |
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141 | |
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142 | /* For each pair of reg classes, |
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143 | a largest reg class contained in their union. */ |
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144 | |
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145 | enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; |
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146 | |
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147 | /* For each pair of reg classes, |
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148 | the smallest reg class containing their union. */ |
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149 | |
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150 | enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; |
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151 | |
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152 | /* Array containing all of the register names */ |
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153 | |
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154 | char *reg_names[] = REGISTER_NAMES; |
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155 | |
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156 | /* For each hard register, the widest mode object that it can contain. |
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157 | This will be a MODE_INT mode if the register can hold integers. Otherwise |
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158 | it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the |
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159 | register. */ |
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160 | |
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161 | enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER]; |
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162 | |
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163 | /* Indexed by n, gives number of times (REG n) is set or clobbered. |
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164 | This information remains valid for the rest of the compilation |
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165 | of the current function; it is used to control register allocation. |
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166 | |
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167 | This information applies to both hard registers and pseudo registers, |
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168 | unlike much of the information above. */ |
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169 | |
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170 | short *reg_n_sets; |
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171 | |
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172 | /* Maximum cost of moving from a register in one class to a register in |
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173 | another class. Based on REGISTER_MOVE_COST. */ |
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174 | |
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175 | static int move_cost[N_REG_CLASSES][N_REG_CLASSES]; |
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176 | |
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177 | /* Similar, but here we don't have to move if the first index is a subset |
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178 | of the second so in that case the cost is zero. */ |
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179 | |
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180 | static int may_move_cost[N_REG_CLASSES][N_REG_CLASSES]; |
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181 | |
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182 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
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183 | |
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184 | /* These are the classes that regs which are auto-incremented or decremented |
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185 | cannot be put in. */ |
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186 | |
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187 | static int forbidden_inc_dec_class[N_REG_CLASSES]; |
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188 | |
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189 | /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec |
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190 | context. */ |
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191 | |
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192 | static char *in_inc_dec; |
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193 | |
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194 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
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195 | |
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196 | /* Function called only once to initialize the above data on reg usage. |
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197 | Once this is done, various switches may override. */ |
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198 | |
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199 | void |
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200 | init_reg_sets () |
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201 | { |
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202 | register int i, j; |
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203 | |
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204 | /* First copy the register information from the initial int form into |
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205 | the regsets. */ |
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206 | |
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207 | for (i = 0; i < N_REG_CLASSES; i++) |
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208 | { |
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209 | CLEAR_HARD_REG_SET (reg_class_contents[i]); |
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210 | |
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211 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) |
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212 | if (int_reg_class_contents[i][j / HOST_BITS_PER_INT] |
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213 | & ((unsigned) 1 << (j % HOST_BITS_PER_INT))) |
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214 | SET_HARD_REG_BIT (reg_class_contents[i], j); |
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215 | } |
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216 | |
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217 | bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs); |
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218 | bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs); |
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219 | bzero (global_regs, sizeof global_regs); |
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220 | |
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221 | /* Compute number of hard regs in each class. */ |
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222 | |
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223 | bzero ((char *) reg_class_size, sizeof reg_class_size); |
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224 | for (i = 0; i < N_REG_CLASSES; i++) |
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225 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) |
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226 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) |
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227 | reg_class_size[i]++; |
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228 | |
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229 | /* Initialize the table of subunions. |
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230 | reg_class_subunion[I][J] gets the largest-numbered reg-class |
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231 | that is contained in the union of classes I and J. */ |
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232 | |
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233 | for (i = 0; i < N_REG_CLASSES; i++) |
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234 | { |
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235 | for (j = 0; j < N_REG_CLASSES; j++) |
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236 | { |
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237 | #ifdef HARD_REG_SET |
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238 | register /* Declare it register if it's a scalar. */ |
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239 | #endif |
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240 | HARD_REG_SET c; |
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241 | register int k; |
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242 | |
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243 | COPY_HARD_REG_SET (c, reg_class_contents[i]); |
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244 | IOR_HARD_REG_SET (c, reg_class_contents[j]); |
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245 | for (k = 0; k < N_REG_CLASSES; k++) |
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246 | { |
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247 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c, |
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248 | subclass1); |
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249 | continue; |
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250 | |
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251 | subclass1: |
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252 | /* keep the largest subclass */ /* SPEE 900308 */ |
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253 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], |
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254 | reg_class_contents[(int) reg_class_subunion[i][j]], |
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255 | subclass2); |
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256 | reg_class_subunion[i][j] = (enum reg_class) k; |
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257 | subclass2: |
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258 | ; |
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259 | } |
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260 | } |
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261 | } |
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262 | |
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263 | /* Initialize the table of superunions. |
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264 | reg_class_superunion[I][J] gets the smallest-numbered reg-class |
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265 | containing the union of classes I and J. */ |
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266 | |
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267 | for (i = 0; i < N_REG_CLASSES; i++) |
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268 | { |
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269 | for (j = 0; j < N_REG_CLASSES; j++) |
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270 | { |
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271 | #ifdef HARD_REG_SET |
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272 | register /* Declare it register if it's a scalar. */ |
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273 | #endif |
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274 | HARD_REG_SET c; |
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275 | register int k; |
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276 | |
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277 | COPY_HARD_REG_SET (c, reg_class_contents[i]); |
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278 | IOR_HARD_REG_SET (c, reg_class_contents[j]); |
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279 | for (k = 0; k < N_REG_CLASSES; k++) |
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280 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass); |
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281 | |
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282 | superclass: |
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283 | reg_class_superunion[i][j] = (enum reg_class) k; |
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284 | } |
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285 | } |
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286 | |
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287 | /* Initialize the tables of subclasses and superclasses of each reg class. |
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288 | First clear the whole table, then add the elements as they are found. */ |
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289 | |
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290 | for (i = 0; i < N_REG_CLASSES; i++) |
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291 | { |
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292 | for (j = 0; j < N_REG_CLASSES; j++) |
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293 | { |
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294 | reg_class_superclasses[i][j] = LIM_REG_CLASSES; |
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295 | reg_class_subclasses[i][j] = LIM_REG_CLASSES; |
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296 | } |
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297 | } |
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298 | |
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299 | for (i = 0; i < N_REG_CLASSES; i++) |
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300 | { |
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301 | if (i == (int) NO_REGS) |
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302 | continue; |
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303 | |
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304 | for (j = i + 1; j < N_REG_CLASSES; j++) |
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305 | { |
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306 | enum reg_class *p; |
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307 | |
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308 | GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j], |
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309 | subclass); |
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310 | continue; |
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311 | subclass: |
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312 | /* Reg class I is a subclass of J. |
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313 | Add J to the table of superclasses of I. */ |
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314 | p = ®_class_superclasses[i][0]; |
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315 | while (*p != LIM_REG_CLASSES) p++; |
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316 | *p = (enum reg_class) j; |
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317 | /* Add I to the table of superclasses of J. */ |
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318 | p = ®_class_subclasses[j][0]; |
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319 | while (*p != LIM_REG_CLASSES) p++; |
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320 | *p = (enum reg_class) i; |
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321 | } |
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322 | } |
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323 | |
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324 | /* Initialize the move cost table. Find every subset of each class |
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325 | and take the maximum cost of moving any subset to any other. */ |
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326 | |
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327 | for (i = 0; i < N_REG_CLASSES; i++) |
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328 | for (j = 0; j < N_REG_CLASSES; j++) |
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329 | { |
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330 | int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j); |
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331 | enum reg_class *p1, *p2; |
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332 | |
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333 | for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++) |
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334 | if (*p2 != i) |
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335 | cost = MAX (cost, REGISTER_MOVE_COST (i, *p2)); |
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336 | |
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337 | for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++) |
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338 | { |
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339 | if (*p1 != j) |
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340 | cost = MAX (cost, REGISTER_MOVE_COST (*p1, j)); |
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341 | |
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342 | for (p2 = ®_class_subclasses[j][0]; |
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343 | *p2 != LIM_REG_CLASSES; p2++) |
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344 | if (*p1 != *p2) |
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345 | cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2)); |
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346 | } |
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347 | |
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348 | move_cost[i][j] = cost; |
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349 | |
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350 | if (reg_class_subset_p (i, j)) |
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351 | cost = 0; |
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352 | |
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353 | may_move_cost[i][j] = cost; |
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354 | } |
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355 | } |
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356 | |
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357 | /* After switches have been processed, which perhaps alter |
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358 | `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ |
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359 | |
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360 | static void |
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361 | init_reg_sets_1 () |
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362 | { |
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363 | register int i; |
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364 | |
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365 | /* This macro allows the fixed or call-used registers |
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366 | to depend on target flags. */ |
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367 | |
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368 | #ifdef CONDITIONAL_REGISTER_USAGE |
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369 | CONDITIONAL_REGISTER_USAGE; |
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370 | #endif |
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371 | |
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372 | /* Initialize "constant" tables. */ |
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373 | |
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374 | CLEAR_HARD_REG_SET (fixed_reg_set); |
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375 | CLEAR_HARD_REG_SET (call_used_reg_set); |
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376 | CLEAR_HARD_REG_SET (call_fixed_reg_set); |
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377 | |
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378 | bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs); |
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379 | |
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380 | n_non_fixed_regs = 0; |
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381 | |
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382 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
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383 | { |
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384 | if (fixed_regs[i]) |
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385 | SET_HARD_REG_BIT (fixed_reg_set, i); |
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386 | else |
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387 | n_non_fixed_regs++; |
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388 | |
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389 | if (call_used_regs[i]) |
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390 | SET_HARD_REG_BIT (call_used_reg_set, i); |
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391 | if (call_fixed_regs[i]) |
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392 | SET_HARD_REG_BIT (call_fixed_reg_set, i); |
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393 | } |
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394 | } |
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395 | |
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396 | /* Compute the table of register modes. |
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397 | These values are used to record death information for individual registers |
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398 | (as opposed to a multi-register mode). */ |
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399 | |
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400 | static void |
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401 | init_reg_modes () |
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402 | { |
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403 | register int i; |
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404 | |
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405 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
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406 | { |
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407 | reg_raw_mode[i] = choose_hard_reg_mode (i, 1); |
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408 | |
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409 | /* If we couldn't find a valid mode, fall back to `word_mode'. |
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410 | ??? We assume `word_mode' has already been initialized. |
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411 | ??? One situation in which we need to do this is on the mips where |
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412 | HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like |
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413 | to use DF mode for the even registers and VOIDmode for the odd |
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414 | (for the cpu models where the odd ones are inaccessible). */ |
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415 | if (reg_raw_mode[i] == VOIDmode) |
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416 | reg_raw_mode[i] = word_mode; |
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417 | } |
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418 | } |
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419 | |
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420 | /* Finish initializing the register sets and |
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421 | initialize the register modes. */ |
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422 | |
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423 | void |
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424 | init_regs () |
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425 | { |
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426 | /* This finishes what was started by init_reg_sets, but couldn't be done |
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427 | until after register usage was specified. */ |
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428 | if (!output_bytecode) |
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429 | init_reg_sets_1 (); |
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430 | |
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431 | init_reg_modes (); |
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432 | } |
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433 | |
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434 | /* Return a machine mode that is legitimate for hard reg REGNO and large |
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435 | enough to save nregs. If we can't find one, return VOIDmode. */ |
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436 | |
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437 | enum machine_mode |
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438 | choose_hard_reg_mode (regno, nregs) |
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439 | int regno; |
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440 | int nregs; |
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441 | { |
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442 | enum machine_mode found_mode = VOIDmode, mode; |
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443 | |
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444 | /* We first look for the largest integer mode that can be validly |
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445 | held in REGNO. If none, we look for the largest floating-point mode. |
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446 | If we still didn't find a valid mode, try CCmode. */ |
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447 | |
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448 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); |
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449 | mode != VOIDmode; |
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450 | mode = GET_MODE_WIDER_MODE (mode)) |
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451 | if (HARD_REGNO_NREGS (regno, mode) == nregs |
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452 | && HARD_REGNO_MODE_OK (regno, mode)) |
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453 | found_mode = mode; |
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454 | |
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455 | if (found_mode != VOIDmode) |
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456 | return found_mode; |
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457 | |
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458 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); |
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459 | mode != VOIDmode; |
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460 | mode = GET_MODE_WIDER_MODE (mode)) |
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461 | if (HARD_REGNO_NREGS (regno, mode) == nregs |
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462 | && HARD_REGNO_MODE_OK (regno, mode)) |
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463 | found_mode = mode; |
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464 | |
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465 | if (found_mode != VOIDmode) |
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466 | return found_mode; |
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467 | |
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468 | if (HARD_REGNO_NREGS (regno, CCmode) == nregs |
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469 | && HARD_REGNO_MODE_OK (regno, CCmode)) |
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470 | return CCmode; |
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471 | |
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472 | /* We can't find a mode valid for this register. */ |
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473 | return VOIDmode; |
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474 | } |
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475 | |
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476 | /* Specify the usage characteristics of the register named NAME. |
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477 | It should be a fixed register if FIXED and a |
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478 | call-used register if CALL_USED. */ |
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479 | |
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480 | void |
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481 | fix_register (name, fixed, call_used) |
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482 | char *name; |
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483 | int fixed, call_used; |
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484 | { |
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485 | int i; |
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486 | |
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487 | if (output_bytecode) |
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488 | { |
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489 | warning ("request to mark `%s' as %s ignored by bytecode compiler", |
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490 | name, call_used ? "call-used" : "fixed"); |
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491 | return; |
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492 | } |
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493 | |
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494 | /* Decode the name and update the primary form of |
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495 | the register info. */ |
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496 | |
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497 | if ((i = decode_reg_name (name)) >= 0) |
---|
498 | { |
---|
499 | fixed_regs[i] = fixed; |
---|
500 | call_used_regs[i] = call_used; |
---|
501 | } |
---|
502 | else |
---|
503 | { |
---|
504 | warning ("unknown register name: %s", name); |
---|
505 | } |
---|
506 | } |
---|
507 | |
---|
508 | /* Mark register number I as global. */ |
---|
509 | |
---|
510 | void |
---|
511 | globalize_reg (i) |
---|
512 | int i; |
---|
513 | { |
---|
514 | if (global_regs[i]) |
---|
515 | { |
---|
516 | warning ("register used for two global register variables"); |
---|
517 | return; |
---|
518 | } |
---|
519 | |
---|
520 | if (call_used_regs[i] && ! fixed_regs[i]) |
---|
521 | warning ("call-clobbered register used for global register variable"); |
---|
522 | |
---|
523 | global_regs[i] = 1; |
---|
524 | |
---|
525 | /* If already fixed, nothing else to do. */ |
---|
526 | if (fixed_regs[i]) |
---|
527 | return; |
---|
528 | |
---|
529 | fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; |
---|
530 | n_non_fixed_regs--; |
---|
531 | |
---|
532 | SET_HARD_REG_BIT (fixed_reg_set, i); |
---|
533 | SET_HARD_REG_BIT (call_used_reg_set, i); |
---|
534 | SET_HARD_REG_BIT (call_fixed_reg_set, i); |
---|
535 | } |
---|
536 | |
---|
537 | /* Now the data and code for the `regclass' pass, which happens |
---|
538 | just before local-alloc. */ |
---|
539 | |
---|
540 | /* The `costs' struct records the cost of using a hard register of each class |
---|
541 | and of using memory for each pseudo. We use this data to set up |
---|
542 | register class preferences. */ |
---|
543 | |
---|
544 | struct costs |
---|
545 | { |
---|
546 | int cost[N_REG_CLASSES]; |
---|
547 | int mem_cost; |
---|
548 | }; |
---|
549 | |
---|
550 | /* Record the cost of each class for each pseudo. */ |
---|
551 | |
---|
552 | static struct costs *costs; |
---|
553 | |
---|
554 | /* Record the same data by operand number, accumulated for each alternative |
---|
555 | in an insn. The contribution to a pseudo is that of the minimum-cost |
---|
556 | alternative. */ |
---|
557 | |
---|
558 | static struct costs op_costs[MAX_RECOG_OPERANDS]; |
---|
559 | |
---|
560 | /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R. |
---|
561 | This is available after `regclass' is run. */ |
---|
562 | |
---|
563 | static char *prefclass; |
---|
564 | |
---|
565 | /* altclass[R] is a register class that we should use for allocating |
---|
566 | pseudo number R if no register in the preferred class is available. |
---|
567 | If no register in this class is available, memory is preferred. |
---|
568 | |
---|
569 | It might appear to be more general to have a bitmask of classes here, |
---|
570 | but since it is recommended that there be a class corresponding to the |
---|
571 | union of most major pair of classes, that generality is not required. |
---|
572 | |
---|
573 | This is available after `regclass' is run. */ |
---|
574 | |
---|
575 | static char *altclass; |
---|
576 | |
---|
577 | /* Record the depth of loops that we are in. */ |
---|
578 | |
---|
579 | static int loop_depth; |
---|
580 | |
---|
581 | /* Account for the fact that insns within a loop are executed very commonly, |
---|
582 | but don't keep doing this as loops go too deep. */ |
---|
583 | |
---|
584 | static int loop_cost; |
---|
585 | |
---|
586 | static void record_reg_classes PROTO((int, int, rtx *, enum machine_mode *, |
---|
587 | char **, rtx)); |
---|
588 | static int copy_cost PROTO((rtx, enum machine_mode, |
---|
589 | enum reg_class, int)); |
---|
590 | static void record_address_regs PROTO((rtx, enum reg_class, int)); |
---|
591 | static auto_inc_dec_reg_p PROTO((rtx, enum machine_mode)); |
---|
592 | static void reg_scan_mark_refs PROTO((rtx, rtx, int)); |
---|
593 | |
---|
594 | /* Return the reg_class in which pseudo reg number REGNO is best allocated. |
---|
595 | This function is sometimes called before the info has been computed. |
---|
596 | When that happens, just return GENERAL_REGS, which is innocuous. */ |
---|
597 | |
---|
598 | enum reg_class |
---|
599 | reg_preferred_class (regno) |
---|
600 | int regno; |
---|
601 | { |
---|
602 | if (prefclass == 0) |
---|
603 | return GENERAL_REGS; |
---|
604 | return (enum reg_class) prefclass[regno]; |
---|
605 | } |
---|
606 | |
---|
607 | enum reg_class |
---|
608 | reg_alternate_class (regno) |
---|
609 | { |
---|
610 | if (prefclass == 0) |
---|
611 | return ALL_REGS; |
---|
612 | |
---|
613 | return (enum reg_class) altclass[regno]; |
---|
614 | } |
---|
615 | |
---|
616 | /* This prevents dump_flow_info from losing if called |
---|
617 | before regclass is run. */ |
---|
618 | |
---|
619 | void |
---|
620 | regclass_init () |
---|
621 | { |
---|
622 | prefclass = 0; |
---|
623 | } |
---|
624 | |
---|
625 | /* This is a pass of the compiler that scans all instructions |
---|
626 | and calculates the preferred class for each pseudo-register. |
---|
627 | This information can be accessed later by calling `reg_preferred_class'. |
---|
628 | This pass comes just before local register allocation. */ |
---|
629 | |
---|
630 | void |
---|
631 | regclass (f, nregs) |
---|
632 | rtx f; |
---|
633 | int nregs; |
---|
634 | { |
---|
635 | #ifdef REGISTER_CONSTRAINTS |
---|
636 | register rtx insn; |
---|
637 | register int i, j; |
---|
638 | struct costs init_cost; |
---|
639 | rtx set; |
---|
640 | int pass; |
---|
641 | |
---|
642 | init_recog (); |
---|
643 | |
---|
644 | costs = (struct costs *) alloca (nregs * sizeof (struct costs)); |
---|
645 | |
---|
646 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
---|
647 | |
---|
648 | in_inc_dec = (char *) alloca (nregs); |
---|
649 | |
---|
650 | /* Initialize information about which register classes can be used for |
---|
651 | pseudos that are auto-incremented or auto-decremented. It would |
---|
652 | seem better to put this in init_reg_sets, but we need to be able |
---|
653 | to allocate rtx, which we can't do that early. */ |
---|
654 | |
---|
655 | for (i = 0; i < N_REG_CLASSES; i++) |
---|
656 | { |
---|
657 | rtx r = gen_rtx (REG, VOIDmode, 0); |
---|
658 | enum machine_mode m; |
---|
659 | |
---|
660 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) |
---|
661 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) |
---|
662 | { |
---|
663 | REGNO (r) = j; |
---|
664 | |
---|
665 | for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE; |
---|
666 | m = (enum machine_mode) ((int) m + 1)) |
---|
667 | if (HARD_REGNO_MODE_OK (j, m)) |
---|
668 | { |
---|
669 | PUT_MODE (r, m); |
---|
670 | |
---|
671 | /* If a register is not directly suitable for an |
---|
672 | auto-increment or decrement addressing mode and |
---|
673 | requires secondary reloads, disallow its class from |
---|
674 | being used in such addresses. */ |
---|
675 | |
---|
676 | if ((0 |
---|
677 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
---|
678 | || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) |
---|
679 | != NO_REGS) |
---|
680 | #endif |
---|
681 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
---|
682 | || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) |
---|
683 | != NO_REGS) |
---|
684 | #endif |
---|
685 | ) |
---|
686 | && ! auto_inc_dec_reg_p (r, m)) |
---|
687 | forbidden_inc_dec_class[i] = 1; |
---|
688 | } |
---|
689 | } |
---|
690 | } |
---|
691 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
---|
692 | |
---|
693 | init_cost.mem_cost = 10000; |
---|
694 | for (i = 0; i < N_REG_CLASSES; i++) |
---|
695 | init_cost.cost[i] = 10000; |
---|
696 | |
---|
697 | /* Normally we scan the insns once and determine the best class to use for |
---|
698 | each register. However, if -fexpensive_optimizations are on, we do so |
---|
699 | twice, the second time using the tentative best classes to guide the |
---|
700 | selection. */ |
---|
701 | |
---|
702 | for (pass = 0; pass <= flag_expensive_optimizations; pass++) |
---|
703 | { |
---|
704 | /* Zero out our accumulation of the cost of each class for each reg. */ |
---|
705 | |
---|
706 | bzero ((char *) costs, nregs * sizeof (struct costs)); |
---|
707 | |
---|
708 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
---|
709 | bzero (in_inc_dec, nregs); |
---|
710 | #endif |
---|
711 | |
---|
712 | loop_depth = 0, loop_cost = 1; |
---|
713 | |
---|
714 | /* Scan the instructions and record each time it would |
---|
715 | save code to put a certain register in a certain class. */ |
---|
716 | |
---|
717 | for (insn = f; insn; insn = NEXT_INSN (insn)) |
---|
718 | { |
---|
719 | char *constraints[MAX_RECOG_OPERANDS]; |
---|
720 | enum machine_mode modes[MAX_RECOG_OPERANDS]; |
---|
721 | int nalternatives; |
---|
722 | int noperands; |
---|
723 | |
---|
724 | /* Show that an insn inside a loop is likely to be executed three |
---|
725 | times more than insns outside a loop. This is much more aggressive |
---|
726 | than the assumptions made elsewhere and is being tried as an |
---|
727 | experiment. */ |
---|
728 | |
---|
729 | if (GET_CODE (insn) == NOTE |
---|
730 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) |
---|
731 | loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5)); |
---|
732 | else if (GET_CODE (insn) == NOTE |
---|
733 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) |
---|
734 | loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5)); |
---|
735 | |
---|
736 | else if ((GET_CODE (insn) == INSN |
---|
737 | && GET_CODE (PATTERN (insn)) != USE |
---|
738 | && GET_CODE (PATTERN (insn)) != CLOBBER |
---|
739 | && GET_CODE (PATTERN (insn)) != ASM_INPUT) |
---|
740 | || (GET_CODE (insn) == JUMP_INSN |
---|
741 | && GET_CODE (PATTERN (insn)) != ADDR_VEC |
---|
742 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC) |
---|
743 | || GET_CODE (insn) == CALL_INSN) |
---|
744 | { |
---|
745 | if (GET_CODE (insn) == INSN |
---|
746 | && (noperands = asm_noperands (PATTERN (insn))) >= 0) |
---|
747 | { |
---|
748 | decode_asm_operands (PATTERN (insn), recog_operand, NULL_PTR, |
---|
749 | constraints, modes); |
---|
750 | nalternatives = (noperands == 0 ? 0 |
---|
751 | : n_occurrences (',', constraints[0]) + 1); |
---|
752 | } |
---|
753 | else |
---|
754 | { |
---|
755 | int insn_code_number = recog_memoized (insn); |
---|
756 | rtx note; |
---|
757 | |
---|
758 | set = single_set (insn); |
---|
759 | insn_extract (insn); |
---|
760 | |
---|
761 | nalternatives = insn_n_alternatives[insn_code_number]; |
---|
762 | noperands = insn_n_operands[insn_code_number]; |
---|
763 | |
---|
764 | /* If this insn loads a parameter from its stack slot, then |
---|
765 | it represents a savings, rather than a cost, if the |
---|
766 | parameter is stored in memory. Record this fact. */ |
---|
767 | |
---|
768 | if (set != 0 && GET_CODE (SET_DEST (set)) == REG |
---|
769 | && GET_CODE (SET_SRC (set)) == MEM |
---|
770 | && (note = find_reg_note (insn, REG_EQUIV, |
---|
771 | NULL_RTX)) != 0 |
---|
772 | && GET_CODE (XEXP (note, 0)) == MEM) |
---|
773 | { |
---|
774 | costs[REGNO (SET_DEST (set))].mem_cost |
---|
775 | -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set))) |
---|
776 | * loop_cost); |
---|
777 | record_address_regs (XEXP (SET_SRC (set), 0), |
---|
778 | BASE_REG_CLASS, loop_cost * 2); |
---|
779 | continue; |
---|
780 | } |
---|
781 | |
---|
782 | /* Improve handling of two-address insns such as |
---|
783 | (set X (ashift CONST Y)) where CONST must be made to |
---|
784 | match X. Change it into two insns: (set X CONST) |
---|
785 | (set X (ashift X Y)). If we left this for reloading, it |
---|
786 | would probably get three insns because X and Y might go |
---|
787 | in the same place. This prevents X and Y from receiving |
---|
788 | the same hard reg. |
---|
789 | |
---|
790 | We can only do this if the modes of operands 0 and 1 |
---|
791 | (which might not be the same) are tieable and we only need |
---|
792 | do this during our first pass. */ |
---|
793 | |
---|
794 | if (pass == 0 && optimize |
---|
795 | && noperands >= 3 |
---|
796 | && insn_operand_constraint[insn_code_number][1][0] == '0' |
---|
797 | && insn_operand_constraint[insn_code_number][1][1] == 0 |
---|
798 | && CONSTANT_P (recog_operand[1]) |
---|
799 | && ! rtx_equal_p (recog_operand[0], recog_operand[1]) |
---|
800 | && ! rtx_equal_p (recog_operand[0], recog_operand[2]) |
---|
801 | && GET_CODE (recog_operand[0]) == REG |
---|
802 | && MODES_TIEABLE_P (GET_MODE (recog_operand[0]), |
---|
803 | insn_operand_mode[insn_code_number][1])) |
---|
804 | { |
---|
805 | rtx previnsn = prev_real_insn (insn); |
---|
806 | rtx dest |
---|
807 | = gen_lowpart (insn_operand_mode[insn_code_number][1], |
---|
808 | recog_operand[0]); |
---|
809 | rtx newinsn |
---|
810 | = emit_insn_before (gen_move_insn (dest, |
---|
811 | recog_operand[1]), |
---|
812 | insn); |
---|
813 | |
---|
814 | /* If this insn was the start of a basic block, |
---|
815 | include the new insn in that block. |
---|
816 | We need not check for code_label here; |
---|
817 | while a basic block can start with a code_label, |
---|
818 | INSN could not be at the beginning of that block. */ |
---|
819 | if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN) |
---|
820 | { |
---|
821 | int b; |
---|
822 | for (b = 0; b < n_basic_blocks; b++) |
---|
823 | if (insn == basic_block_head[b]) |
---|
824 | basic_block_head[b] = newinsn; |
---|
825 | } |
---|
826 | |
---|
827 | /* This makes one more setting of new insns's dest. */ |
---|
828 | reg_n_sets[REGNO (recog_operand[0])]++; |
---|
829 | |
---|
830 | *recog_operand_loc[1] = recog_operand[0]; |
---|
831 | for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--) |
---|
832 | if (recog_dup_num[i] == 1) |
---|
833 | *recog_dup_loc[i] = recog_operand[0]; |
---|
834 | |
---|
835 | insn = PREV_INSN (newinsn); |
---|
836 | continue; |
---|
837 | } |
---|
838 | |
---|
839 | for (i = 0; i < noperands; i++) |
---|
840 | { |
---|
841 | constraints[i] |
---|
842 | = insn_operand_constraint[insn_code_number][i]; |
---|
843 | modes[i] = insn_operand_mode[insn_code_number][i]; |
---|
844 | } |
---|
845 | } |
---|
846 | |
---|
847 | /* If we get here, we are set up to record the costs of all the |
---|
848 | operands for this insn. Start by initializing the costs. |
---|
849 | Then handle any address registers. Finally record the desired |
---|
850 | classes for any pseudos, doing it twice if some pair of |
---|
851 | operands are commutative. */ |
---|
852 | |
---|
853 | for (i = 0; i < noperands; i++) |
---|
854 | { |
---|
855 | op_costs[i] = init_cost; |
---|
856 | |
---|
857 | if (GET_CODE (recog_operand[i]) == SUBREG) |
---|
858 | recog_operand[i] = SUBREG_REG (recog_operand[i]); |
---|
859 | |
---|
860 | if (GET_CODE (recog_operand[i]) == MEM) |
---|
861 | record_address_regs (XEXP (recog_operand[i], 0), |
---|
862 | BASE_REG_CLASS, loop_cost * 2); |
---|
863 | else if (constraints[i][0] == 'p') |
---|
864 | record_address_regs (recog_operand[i], |
---|
865 | BASE_REG_CLASS, loop_cost * 2); |
---|
866 | } |
---|
867 | |
---|
868 | /* Check for commutative in a separate loop so everything will |
---|
869 | have been initialized. We must do this even if one operand |
---|
870 | is a constant--see addsi3 in m68k.md. */ |
---|
871 | |
---|
872 | for (i = 0; i < noperands - 1; i++) |
---|
873 | if (constraints[i][0] == '%') |
---|
874 | { |
---|
875 | char *xconstraints[MAX_RECOG_OPERANDS]; |
---|
876 | int j; |
---|
877 | |
---|
878 | /* Handle commutative operands by swapping the constraints. |
---|
879 | We assume the modes are the same. */ |
---|
880 | |
---|
881 | for (j = 0; j < noperands; j++) |
---|
882 | xconstraints[j] = constraints[j]; |
---|
883 | |
---|
884 | xconstraints[i] = constraints[i+1]; |
---|
885 | xconstraints[i+1] = constraints[i]; |
---|
886 | record_reg_classes (nalternatives, noperands, |
---|
887 | recog_operand, modes, xconstraints, |
---|
888 | insn); |
---|
889 | } |
---|
890 | |
---|
891 | record_reg_classes (nalternatives, noperands, recog_operand, |
---|
892 | modes, constraints, insn); |
---|
893 | |
---|
894 | /* Now add the cost for each operand to the total costs for |
---|
895 | its register. */ |
---|
896 | |
---|
897 | for (i = 0; i < noperands; i++) |
---|
898 | if (GET_CODE (recog_operand[i]) == REG |
---|
899 | && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER) |
---|
900 | { |
---|
901 | int regno = REGNO (recog_operand[i]); |
---|
902 | struct costs *p = &costs[regno], *q = &op_costs[i]; |
---|
903 | |
---|
904 | p->mem_cost += q->mem_cost * loop_cost; |
---|
905 | for (j = 0; j < N_REG_CLASSES; j++) |
---|
906 | p->cost[j] += q->cost[j] * loop_cost; |
---|
907 | } |
---|
908 | } |
---|
909 | } |
---|
910 | |
---|
911 | /* Now for each register look at how desirable each class is |
---|
912 | and find which class is preferred. Store that in |
---|
913 | `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register |
---|
914 | class any of whose registers is better than memory. */ |
---|
915 | |
---|
916 | if (pass == 0) |
---|
917 | { |
---|
918 | prefclass = (char *) oballoc (nregs); |
---|
919 | altclass = (char *) oballoc (nregs); |
---|
920 | } |
---|
921 | |
---|
922 | for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) |
---|
923 | { |
---|
924 | register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; |
---|
925 | enum reg_class best = ALL_REGS, alt = NO_REGS; |
---|
926 | /* This is an enum reg_class, but we call it an int |
---|
927 | to save lots of casts. */ |
---|
928 | register int class; |
---|
929 | register struct costs *p = &costs[i]; |
---|
930 | |
---|
931 | for (class = (int) ALL_REGS - 1; class > 0; class--) |
---|
932 | { |
---|
933 | /* Ignore classes that are too small for this operand or |
---|
934 | invalid for a operand that was auto-incremented. */ |
---|
935 | if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i)) |
---|
936 | > reg_class_size[class] |
---|
937 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
---|
938 | || (in_inc_dec[i] && forbidden_inc_dec_class[class]) |
---|
939 | #endif |
---|
940 | ) |
---|
941 | ; |
---|
942 | else if (p->cost[class] < best_cost) |
---|
943 | { |
---|
944 | best_cost = p->cost[class]; |
---|
945 | best = (enum reg_class) class; |
---|
946 | } |
---|
947 | else if (p->cost[class] == best_cost) |
---|
948 | best = reg_class_subunion[(int)best][class]; |
---|
949 | } |
---|
950 | |
---|
951 | /* Record the alternate register class; i.e., a class for which |
---|
952 | every register in it is better than using memory. If adding a |
---|
953 | class would make a smaller class (i.e., no union of just those |
---|
954 | classes exists), skip that class. The major unions of classes |
---|
955 | should be provided as a register class. Don't do this if we |
---|
956 | will be doing it again later. */ |
---|
957 | |
---|
958 | if (pass == 1 || ! flag_expensive_optimizations) |
---|
959 | for (class = 0; class < N_REG_CLASSES; class++) |
---|
960 | if (p->cost[class] < p->mem_cost |
---|
961 | && (reg_class_size[(int) reg_class_subunion[(int) alt][class]] |
---|
962 | > reg_class_size[(int) alt]) |
---|
963 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
---|
964 | && ! (in_inc_dec[i] && forbidden_inc_dec_class[class]) |
---|
965 | #endif |
---|
966 | ) |
---|
967 | alt = reg_class_subunion[(int) alt][class]; |
---|
968 | |
---|
969 | /* If we don't add any classes, nothing to try. */ |
---|
970 | if (alt == best) |
---|
971 | alt = (int) NO_REGS; |
---|
972 | |
---|
973 | /* We cast to (int) because (char) hits bugs in some compilers. */ |
---|
974 | prefclass[i] = (int) best; |
---|
975 | altclass[i] = (int) alt; |
---|
976 | } |
---|
977 | } |
---|
978 | #endif /* REGISTER_CONSTRAINTS */ |
---|
979 | } |
---|
980 | |
---|
981 | #ifdef REGISTER_CONSTRAINTS |
---|
982 | |
---|
983 | /* Record the cost of using memory or registers of various classes for |
---|
984 | the operands in INSN. |
---|
985 | |
---|
986 | N_ALTS is the number of alternatives. |
---|
987 | |
---|
988 | N_OPS is the number of operands. |
---|
989 | |
---|
990 | OPS is an array of the operands. |
---|
991 | |
---|
992 | MODES are the modes of the operands, in case any are VOIDmode. |
---|
993 | |
---|
994 | CONSTRAINTS are the constraints to use for the operands. This array |
---|
995 | is modified by this procedure. |
---|
996 | |
---|
997 | This procedure works alternative by alternative. For each alternative |
---|
998 | we assume that we will be able to allocate all pseudos to their ideal |
---|
999 | register class and calculate the cost of using that alternative. Then |
---|
1000 | we compute for each operand that is a pseudo-register, the cost of |
---|
1001 | having the pseudo allocated to each register class and using it in that |
---|
1002 | alternative. To this cost is added the cost of the alternative. |
---|
1003 | |
---|
1004 | The cost of each class for this insn is its lowest cost among all the |
---|
1005 | alternatives. */ |
---|
1006 | |
---|
1007 | static void |
---|
1008 | record_reg_classes (n_alts, n_ops, ops, modes, constraints, insn) |
---|
1009 | int n_alts; |
---|
1010 | int n_ops; |
---|
1011 | rtx *ops; |
---|
1012 | enum machine_mode *modes; |
---|
1013 | char **constraints; |
---|
1014 | rtx insn; |
---|
1015 | { |
---|
1016 | int alt; |
---|
1017 | enum op_type {OP_READ, OP_WRITE, OP_READ_WRITE} op_types[MAX_RECOG_OPERANDS]; |
---|
1018 | int i, j; |
---|
1019 | rtx set; |
---|
1020 | |
---|
1021 | /* By default, each operand is an input operand. */ |
---|
1022 | |
---|
1023 | for (i = 0; i < n_ops; i++) |
---|
1024 | op_types[i] = OP_READ; |
---|
1025 | |
---|
1026 | /* Process each alternative, each time minimizing an operand's cost with |
---|
1027 | the cost for each operand in that alternative. */ |
---|
1028 | |
---|
1029 | for (alt = 0; alt < n_alts; alt++) |
---|
1030 | { |
---|
1031 | struct costs this_op_costs[MAX_RECOG_OPERANDS]; |
---|
1032 | int alt_fail = 0; |
---|
1033 | int alt_cost = 0; |
---|
1034 | enum reg_class classes[MAX_RECOG_OPERANDS]; |
---|
1035 | int class; |
---|
1036 | |
---|
1037 | for (i = 0; i < n_ops; i++) |
---|
1038 | { |
---|
1039 | char *p = constraints[i]; |
---|
1040 | rtx op = ops[i]; |
---|
1041 | enum machine_mode mode = modes[i]; |
---|
1042 | int allows_mem = 0; |
---|
1043 | int win = 0; |
---|
1044 | char c; |
---|
1045 | |
---|
1046 | /* If this operand has no constraints at all, we can conclude |
---|
1047 | nothing about it since anything is valid. */ |
---|
1048 | |
---|
1049 | if (*p == 0) |
---|
1050 | { |
---|
1051 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) |
---|
1052 | bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]); |
---|
1053 | |
---|
1054 | continue; |
---|
1055 | } |
---|
1056 | |
---|
1057 | if (*p == '%') |
---|
1058 | p++; |
---|
1059 | |
---|
1060 | /* If this alternative is only relevant when this operand |
---|
1061 | matches a previous operand, we do different things depending |
---|
1062 | on whether this operand is a pseudo-reg or not. */ |
---|
1063 | |
---|
1064 | if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) |
---|
1065 | { |
---|
1066 | j = p[0] - '0'; |
---|
1067 | classes[i] = classes[j]; |
---|
1068 | |
---|
1069 | if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER) |
---|
1070 | { |
---|
1071 | /* If this matches the other operand, we have no added |
---|
1072 | cost and we win. */ |
---|
1073 | if (rtx_equal_p (ops[j], op)) |
---|
1074 | win = 1; |
---|
1075 | |
---|
1076 | /* If we can put the other operand into a register, add to |
---|
1077 | the cost of this alternative the cost to copy this |
---|
1078 | operand to the register used for the other operand. */ |
---|
1079 | |
---|
1080 | else if (classes[j] != NO_REGS) |
---|
1081 | alt_cost += copy_cost (op, mode, classes[j], 1), win = 1; |
---|
1082 | } |
---|
1083 | else if (GET_CODE (ops[j]) != REG |
---|
1084 | || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) |
---|
1085 | { |
---|
1086 | /* This op is a pseudo but the one it matches is not. */ |
---|
1087 | |
---|
1088 | /* If we can't put the other operand into a register, this |
---|
1089 | alternative can't be used. */ |
---|
1090 | |
---|
1091 | if (classes[j] == NO_REGS) |
---|
1092 | alt_fail = 1; |
---|
1093 | |
---|
1094 | /* Otherwise, add to the cost of this alternative the cost |
---|
1095 | to copy the other operand to the register used for this |
---|
1096 | operand. */ |
---|
1097 | |
---|
1098 | else |
---|
1099 | alt_cost += copy_cost (ops[j], mode, classes[j], 1); |
---|
1100 | } |
---|
1101 | else |
---|
1102 | { |
---|
1103 | /* The costs of this operand are the same as that of the |
---|
1104 | other operand. However, if we cannot tie them, this |
---|
1105 | alternative needs to do a copy, which is one |
---|
1106 | instruction. */ |
---|
1107 | |
---|
1108 | this_op_costs[i] = this_op_costs[j]; |
---|
1109 | if (REGNO (ops[i]) != REGNO (ops[j]) |
---|
1110 | && ! find_reg_note (insn, REG_DEAD, op)) |
---|
1111 | alt_cost += 2; |
---|
1112 | |
---|
1113 | /* This is in place of ordinary cost computation |
---|
1114 | for this operand, so skip to the end of the |
---|
1115 | alternative (should be just one character). */ |
---|
1116 | while (*p && *p++ != ',') |
---|
1117 | ; |
---|
1118 | |
---|
1119 | constraints[i] = p; |
---|
1120 | continue; |
---|
1121 | } |
---|
1122 | } |
---|
1123 | |
---|
1124 | /* Scan all the constraint letters. See if the operand matches |
---|
1125 | any of the constraints. Collect the valid register classes |
---|
1126 | and see if this operand accepts memory. */ |
---|
1127 | |
---|
1128 | classes[i] = NO_REGS; |
---|
1129 | while (*p && (c = *p++) != ',') |
---|
1130 | switch (c) |
---|
1131 | { |
---|
1132 | case '=': |
---|
1133 | op_types[i] = OP_WRITE; |
---|
1134 | break; |
---|
1135 | |
---|
1136 | case '+': |
---|
1137 | op_types[i] = OP_READ_WRITE; |
---|
1138 | break; |
---|
1139 | |
---|
1140 | case '*': |
---|
1141 | /* Ignore the next letter for this pass. */ |
---|
1142 | p++; |
---|
1143 | break; |
---|
1144 | |
---|
1145 | case '%': |
---|
1146 | case '?': case '!': case '#': |
---|
1147 | case '&': |
---|
1148 | case '0': case '1': case '2': case '3': case '4': |
---|
1149 | case 'p': |
---|
1150 | break; |
---|
1151 | |
---|
1152 | case 'm': case 'o': case 'V': |
---|
1153 | /* It doesn't seem worth distinguishing between offsettable |
---|
1154 | and non-offsettable addresses here. */ |
---|
1155 | allows_mem = 1; |
---|
1156 | if (GET_CODE (op) == MEM) |
---|
1157 | win = 1; |
---|
1158 | break; |
---|
1159 | |
---|
1160 | case '<': |
---|
1161 | if (GET_CODE (op) == MEM |
---|
1162 | && (GET_CODE (XEXP (op, 0)) == PRE_DEC |
---|
1163 | || GET_CODE (XEXP (op, 0)) == POST_DEC)) |
---|
1164 | win = 1; |
---|
1165 | break; |
---|
1166 | |
---|
1167 | case '>': |
---|
1168 | if (GET_CODE (op) == MEM |
---|
1169 | && (GET_CODE (XEXP (op, 0)) == PRE_INC |
---|
1170 | || GET_CODE (XEXP (op, 0)) == POST_INC)) |
---|
1171 | win = 1; |
---|
1172 | break; |
---|
1173 | |
---|
1174 | case 'E': |
---|
1175 | #ifndef REAL_ARITHMETIC |
---|
1176 | /* Match any floating double constant, but only if |
---|
1177 | we can examine the bits of it reliably. */ |
---|
1178 | if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT |
---|
1179 | || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) |
---|
1180 | && GET_MODE (op) != VOIDmode && ! flag_pretend_float) |
---|
1181 | break; |
---|
1182 | #endif |
---|
1183 | if (GET_CODE (op) == CONST_DOUBLE) |
---|
1184 | win = 1; |
---|
1185 | break; |
---|
1186 | |
---|
1187 | case 'F': |
---|
1188 | if (GET_CODE (op) == CONST_DOUBLE) |
---|
1189 | win = 1; |
---|
1190 | break; |
---|
1191 | |
---|
1192 | case 'G': |
---|
1193 | case 'H': |
---|
1194 | if (GET_CODE (op) == CONST_DOUBLE |
---|
1195 | && CONST_DOUBLE_OK_FOR_LETTER_P (op, c)) |
---|
1196 | win = 1; |
---|
1197 | break; |
---|
1198 | |
---|
1199 | case 's': |
---|
1200 | if (GET_CODE (op) == CONST_INT |
---|
1201 | || (GET_CODE (op) == CONST_DOUBLE |
---|
1202 | && GET_MODE (op) == VOIDmode)) |
---|
1203 | break; |
---|
1204 | case 'i': |
---|
1205 | if (CONSTANT_P (op) |
---|
1206 | #ifdef LEGITIMATE_PIC_OPERAND_P |
---|
1207 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) |
---|
1208 | #endif |
---|
1209 | ) |
---|
1210 | win = 1; |
---|
1211 | break; |
---|
1212 | |
---|
1213 | case 'n': |
---|
1214 | if (GET_CODE (op) == CONST_INT |
---|
1215 | || (GET_CODE (op) == CONST_DOUBLE |
---|
1216 | && GET_MODE (op) == VOIDmode)) |
---|
1217 | win = 1; |
---|
1218 | break; |
---|
1219 | |
---|
1220 | case 'I': |
---|
1221 | case 'J': |
---|
1222 | case 'K': |
---|
1223 | case 'L': |
---|
1224 | case 'M': |
---|
1225 | case 'N': |
---|
1226 | case 'O': |
---|
1227 | case 'P': |
---|
1228 | if (GET_CODE (op) == CONST_INT |
---|
1229 | && CONST_OK_FOR_LETTER_P (INTVAL (op), c)) |
---|
1230 | win = 1; |
---|
1231 | break; |
---|
1232 | |
---|
1233 | case 'X': |
---|
1234 | win = 1; |
---|
1235 | break; |
---|
1236 | |
---|
1237 | #ifdef EXTRA_CONSTRAINT |
---|
1238 | case 'Q': |
---|
1239 | case 'R': |
---|
1240 | case 'S': |
---|
1241 | case 'T': |
---|
1242 | case 'U': |
---|
1243 | if (EXTRA_CONSTRAINT (op, c)) |
---|
1244 | win = 1; |
---|
1245 | break; |
---|
1246 | #endif |
---|
1247 | |
---|
1248 | case 'g': |
---|
1249 | if (GET_CODE (op) == MEM |
---|
1250 | || (CONSTANT_P (op) |
---|
1251 | #ifdef LEGITIMATE_PIC_OPERAND_P |
---|
1252 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) |
---|
1253 | #endif |
---|
1254 | )) |
---|
1255 | win = 1; |
---|
1256 | allows_mem = 1; |
---|
1257 | case 'r': |
---|
1258 | classes[i] |
---|
1259 | = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS]; |
---|
1260 | break; |
---|
1261 | |
---|
1262 | default: |
---|
1263 | classes[i] |
---|
1264 | = reg_class_subunion[(int) classes[i]] |
---|
1265 | [(int) REG_CLASS_FROM_LETTER (c)]; |
---|
1266 | } |
---|
1267 | |
---|
1268 | constraints[i] = p; |
---|
1269 | |
---|
1270 | /* How we account for this operand now depends on whether it is a |
---|
1271 | pseudo register or not. If it is, we first check if any |
---|
1272 | register classes are valid. If not, we ignore this alternative, |
---|
1273 | since we want to assume that all pseudos get allocated for |
---|
1274 | register preferencing. If some register class is valid, compute |
---|
1275 | the costs of moving the pseudo into that class. */ |
---|
1276 | |
---|
1277 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) |
---|
1278 | { |
---|
1279 | if (classes[i] == NO_REGS) |
---|
1280 | alt_fail = 1; |
---|
1281 | else |
---|
1282 | { |
---|
1283 | struct costs *pp = &this_op_costs[i]; |
---|
1284 | |
---|
1285 | for (class = 0; class < N_REG_CLASSES; class++) |
---|
1286 | pp->cost[class] = may_move_cost[class][(int) classes[i]]; |
---|
1287 | |
---|
1288 | /* If the alternative actually allows memory, make things |
---|
1289 | a bit cheaper since we won't need an extra insn to |
---|
1290 | load it. */ |
---|
1291 | |
---|
1292 | pp->mem_cost = MEMORY_MOVE_COST (mode) - allows_mem; |
---|
1293 | |
---|
1294 | /* If we have assigned a class to this register in our |
---|
1295 | first pass, add a cost to this alternative corresponding |
---|
1296 | to what we would add if this register were not in the |
---|
1297 | appropriate class. */ |
---|
1298 | |
---|
1299 | if (prefclass) |
---|
1300 | alt_cost |
---|
1301 | += may_move_cost[prefclass[REGNO (op)]][(int) classes[i]]; |
---|
1302 | } |
---|
1303 | } |
---|
1304 | |
---|
1305 | /* Otherwise, if this alternative wins, either because we |
---|
1306 | have already determined that or if we have a hard register of |
---|
1307 | the proper class, there is no cost for this alternative. */ |
---|
1308 | |
---|
1309 | else if (win |
---|
1310 | || (GET_CODE (op) == REG |
---|
1311 | && reg_fits_class_p (op, classes[i], 0, GET_MODE (op)))) |
---|
1312 | ; |
---|
1313 | |
---|
1314 | /* If registers are valid, the cost of this alternative includes |
---|
1315 | copying the object to and/or from a register. */ |
---|
1316 | |
---|
1317 | else if (classes[i] != NO_REGS) |
---|
1318 | { |
---|
1319 | if (op_types[i] != OP_WRITE) |
---|
1320 | alt_cost += copy_cost (op, mode, classes[i], 1); |
---|
1321 | |
---|
1322 | if (op_types[i] != OP_READ) |
---|
1323 | alt_cost += copy_cost (op, mode, classes[i], 0); |
---|
1324 | } |
---|
1325 | |
---|
1326 | /* The only other way this alternative can be used is if this is a |
---|
1327 | constant that could be placed into memory. */ |
---|
1328 | |
---|
1329 | else if (CONSTANT_P (op) && allows_mem) |
---|
1330 | alt_cost += MEMORY_MOVE_COST (mode); |
---|
1331 | else |
---|
1332 | alt_fail = 1; |
---|
1333 | } |
---|
1334 | |
---|
1335 | if (alt_fail) |
---|
1336 | continue; |
---|
1337 | |
---|
1338 | /* Finally, update the costs with the information we've calculated |
---|
1339 | about this alternative. */ |
---|
1340 | |
---|
1341 | for (i = 0; i < n_ops; i++) |
---|
1342 | if (GET_CODE (ops[i]) == REG |
---|
1343 | && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) |
---|
1344 | { |
---|
1345 | struct costs *pp = &op_costs[i], *qq = &this_op_costs[i]; |
---|
1346 | int scale = 1 + (op_types[i] == OP_READ_WRITE); |
---|
1347 | |
---|
1348 | pp->mem_cost = MIN (pp->mem_cost, |
---|
1349 | (qq->mem_cost + alt_cost) * scale); |
---|
1350 | |
---|
1351 | for (class = 0; class < N_REG_CLASSES; class++) |
---|
1352 | pp->cost[class] = MIN (pp->cost[class], |
---|
1353 | (qq->cost[class] + alt_cost) * scale); |
---|
1354 | } |
---|
1355 | } |
---|
1356 | |
---|
1357 | /* If this insn is a single set copying operand 1 to operand 0 |
---|
1358 | and one is a pseudo with the other a hard reg that is in its |
---|
1359 | own register class, set the cost of that register class to -1. */ |
---|
1360 | |
---|
1361 | if ((set = single_set (insn)) != 0 |
---|
1362 | && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set) |
---|
1363 | && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG) |
---|
1364 | for (i = 0; i <= 1; i++) |
---|
1365 | if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) |
---|
1366 | { |
---|
1367 | int regno = REGNO (ops[!i]); |
---|
1368 | enum machine_mode mode = GET_MODE (ops[!i]); |
---|
1369 | int class; |
---|
1370 | int nr; |
---|
1371 | |
---|
1372 | if (regno >= FIRST_PSEUDO_REGISTER && prefclass != 0 |
---|
1373 | && (reg_class_size[prefclass[regno]] |
---|
1374 | == CLASS_MAX_NREGS (prefclass[regno], mode))) |
---|
1375 | op_costs[i].cost[prefclass[regno]] = -1; |
---|
1376 | else if (regno < FIRST_PSEUDO_REGISTER) |
---|
1377 | for (class = 0; class < N_REG_CLASSES; class++) |
---|
1378 | if (TEST_HARD_REG_BIT (reg_class_contents[class], regno) |
---|
1379 | && reg_class_size[class] == CLASS_MAX_NREGS (class, mode)) |
---|
1380 | { |
---|
1381 | if (reg_class_size[class] == 1) |
---|
1382 | op_costs[i].cost[class] = -1; |
---|
1383 | else |
---|
1384 | { |
---|
1385 | for (nr = 0; nr < HARD_REGNO_NREGS(regno, mode); nr++) |
---|
1386 | { |
---|
1387 | if (!TEST_HARD_REG_BIT (reg_class_contents[class], regno + nr)) |
---|
1388 | break; |
---|
1389 | } |
---|
1390 | |
---|
1391 | if (nr == HARD_REGNO_NREGS(regno,mode)) |
---|
1392 | op_costs[i].cost[class] = -1; |
---|
1393 | } |
---|
1394 | } |
---|
1395 | } |
---|
1396 | } |
---|
1397 | |
---|
1398 | /* Compute the cost of loading X into (if TO_P is non-zero) or from (if |
---|
1399 | TO_P is zero) a register of class CLASS in mode MODE. |
---|
1400 | |
---|
1401 | X must not be a pseudo. */ |
---|
1402 | |
---|
1403 | static int |
---|
1404 | copy_cost (x, mode, class, to_p) |
---|
1405 | rtx x; |
---|
1406 | enum machine_mode mode; |
---|
1407 | enum reg_class class; |
---|
1408 | int to_p; |
---|
1409 | { |
---|
1410 | enum reg_class secondary_class = NO_REGS; |
---|
1411 | |
---|
1412 | /* If X is a SCRATCH, there is actually nothing to move since we are |
---|
1413 | assuming optimal allocation. */ |
---|
1414 | |
---|
1415 | if (GET_CODE (x) == SCRATCH) |
---|
1416 | return 0; |
---|
1417 | |
---|
1418 | /* Get the class we will actually use for a reload. */ |
---|
1419 | class = PREFERRED_RELOAD_CLASS (x, class); |
---|
1420 | |
---|
1421 | #ifdef HAVE_SECONDARY_RELOADS |
---|
1422 | /* If we need a secondary reload (we assume here that we are using |
---|
1423 | the secondary reload as an intermediate, not a scratch register), the |
---|
1424 | cost is that to load the input into the intermediate register, then |
---|
1425 | to copy them. We use a special value of TO_P to avoid recursion. */ |
---|
1426 | |
---|
1427 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
---|
1428 | if (to_p == 1) |
---|
1429 | secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x); |
---|
1430 | #endif |
---|
1431 | |
---|
1432 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
---|
1433 | if (! to_p) |
---|
1434 | secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x); |
---|
1435 | #endif |
---|
1436 | |
---|
1437 | if (secondary_class != NO_REGS) |
---|
1438 | return (move_cost[(int) secondary_class][(int) class] |
---|
1439 | + copy_cost (x, mode, secondary_class, 2)); |
---|
1440 | #endif /* HAVE_SECONDARY_RELOADS */ |
---|
1441 | |
---|
1442 | /* For memory, use the memory move cost, for (hard) registers, use the |
---|
1443 | cost to move between the register classes, and use 2 for everything |
---|
1444 | else (constants). */ |
---|
1445 | |
---|
1446 | if (GET_CODE (x) == MEM || class == NO_REGS) |
---|
1447 | return MEMORY_MOVE_COST (mode); |
---|
1448 | |
---|
1449 | else if (GET_CODE (x) == REG) |
---|
1450 | return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class]; |
---|
1451 | |
---|
1452 | else |
---|
1453 | /* If this is a constant, we may eventually want to call rtx_cost here. */ |
---|
1454 | return 2; |
---|
1455 | } |
---|
1456 | |
---|
1457 | /* Record the pseudo registers we must reload into hard registers |
---|
1458 | in a subexpression of a memory address, X. |
---|
1459 | |
---|
1460 | CLASS is the class that the register needs to be in and is either |
---|
1461 | BASE_REG_CLASS or INDEX_REG_CLASS. |
---|
1462 | |
---|
1463 | SCALE is twice the amount to multiply the cost by (it is twice so we |
---|
1464 | can represent half-cost adjustments). */ |
---|
1465 | |
---|
1466 | static void |
---|
1467 | record_address_regs (x, class, scale) |
---|
1468 | rtx x; |
---|
1469 | enum reg_class class; |
---|
1470 | int scale; |
---|
1471 | { |
---|
1472 | register enum rtx_code code = GET_CODE (x); |
---|
1473 | |
---|
1474 | switch (code) |
---|
1475 | { |
---|
1476 | case CONST_INT: |
---|
1477 | case CONST: |
---|
1478 | case CC0: |
---|
1479 | case PC: |
---|
1480 | case SYMBOL_REF: |
---|
1481 | case LABEL_REF: |
---|
1482 | return; |
---|
1483 | |
---|
1484 | case PLUS: |
---|
1485 | /* When we have an address that is a sum, |
---|
1486 | we must determine whether registers are "base" or "index" regs. |
---|
1487 | If there is a sum of two registers, we must choose one to be |
---|
1488 | the "base". Luckily, we can use the REGNO_POINTER_FLAG |
---|
1489 | to make a good choice most of the time. We only need to do this |
---|
1490 | on machines that can have two registers in an address and where |
---|
1491 | the base and index register classes are different. |
---|
1492 | |
---|
1493 | ??? This code used to set REGNO_POINTER_FLAG in some cases, but |
---|
1494 | that seems bogus since it should only be set when we are sure |
---|
1495 | the register is being used as a pointer. */ |
---|
1496 | |
---|
1497 | { |
---|
1498 | rtx arg0 = XEXP (x, 0); |
---|
1499 | rtx arg1 = XEXP (x, 1); |
---|
1500 | register enum rtx_code code0 = GET_CODE (arg0); |
---|
1501 | register enum rtx_code code1 = GET_CODE (arg1); |
---|
1502 | |
---|
1503 | /* Look inside subregs. */ |
---|
1504 | if (code0 == SUBREG) |
---|
1505 | arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); |
---|
1506 | if (code1 == SUBREG) |
---|
1507 | arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); |
---|
1508 | |
---|
1509 | /* If this machine only allows one register per address, it must |
---|
1510 | be in the first operand. */ |
---|
1511 | |
---|
1512 | if (MAX_REGS_PER_ADDRESS == 1) |
---|
1513 | record_address_regs (arg0, class, scale); |
---|
1514 | |
---|
1515 | /* If index and base registers are the same on this machine, just |
---|
1516 | record registers in any non-constant operands. We assume here, |
---|
1517 | as well as in the tests below, that all addresses are in |
---|
1518 | canonical form. */ |
---|
1519 | |
---|
1520 | else if (INDEX_REG_CLASS == BASE_REG_CLASS) |
---|
1521 | { |
---|
1522 | record_address_regs (arg0, class, scale); |
---|
1523 | if (! CONSTANT_P (arg1)) |
---|
1524 | record_address_regs (arg1, class, scale); |
---|
1525 | } |
---|
1526 | |
---|
1527 | /* If the second operand is a constant integer, it doesn't change |
---|
1528 | what class the first operand must be. */ |
---|
1529 | |
---|
1530 | else if (code1 == CONST_INT || code1 == CONST_DOUBLE) |
---|
1531 | record_address_regs (arg0, class, scale); |
---|
1532 | |
---|
1533 | /* If the second operand is a symbolic constant, the first operand |
---|
1534 | must be an index register. */ |
---|
1535 | |
---|
1536 | else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) |
---|
1537 | record_address_regs (arg0, INDEX_REG_CLASS, scale); |
---|
1538 | |
---|
1539 | /* If this the sum of two registers where the first is known to be a |
---|
1540 | pointer, it must be a base register with the second an index. */ |
---|
1541 | |
---|
1542 | else if (code0 == REG && code1 == REG |
---|
1543 | && REGNO_POINTER_FLAG (REGNO (arg0))) |
---|
1544 | { |
---|
1545 | record_address_regs (arg0, BASE_REG_CLASS, scale); |
---|
1546 | record_address_regs (arg1, INDEX_REG_CLASS, scale); |
---|
1547 | } |
---|
1548 | |
---|
1549 | /* If this is the sum of two registers and neither is known to |
---|
1550 | be a pointer, count equal chances that each might be a base |
---|
1551 | or index register. This case should be rare. */ |
---|
1552 | |
---|
1553 | else if (code0 == REG && code1 == REG |
---|
1554 | && ! REGNO_POINTER_FLAG (REGNO (arg0)) |
---|
1555 | && ! REGNO_POINTER_FLAG (REGNO (arg1))) |
---|
1556 | { |
---|
1557 | record_address_regs (arg0, BASE_REG_CLASS, scale / 2); |
---|
1558 | record_address_regs (arg0, INDEX_REG_CLASS, scale / 2); |
---|
1559 | record_address_regs (arg1, BASE_REG_CLASS, scale / 2); |
---|
1560 | record_address_regs (arg1, INDEX_REG_CLASS, scale / 2); |
---|
1561 | } |
---|
1562 | |
---|
1563 | /* In all other cases, the first operand is an index and the |
---|
1564 | second is the base. */ |
---|
1565 | |
---|
1566 | else |
---|
1567 | { |
---|
1568 | record_address_regs (arg0, INDEX_REG_CLASS, scale); |
---|
1569 | record_address_regs (arg1, BASE_REG_CLASS, scale); |
---|
1570 | } |
---|
1571 | } |
---|
1572 | break; |
---|
1573 | |
---|
1574 | case POST_INC: |
---|
1575 | case PRE_INC: |
---|
1576 | case POST_DEC: |
---|
1577 | case PRE_DEC: |
---|
1578 | /* Double the importance of a pseudo register that is incremented |
---|
1579 | or decremented, since it would take two extra insns |
---|
1580 | if it ends up in the wrong place. If the operand is a pseudo, |
---|
1581 | show it is being used in an INC_DEC context. */ |
---|
1582 | |
---|
1583 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
---|
1584 | if (GET_CODE (XEXP (x, 0)) == REG |
---|
1585 | && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) |
---|
1586 | in_inc_dec[REGNO (XEXP (x, 0))] = 1; |
---|
1587 | #endif |
---|
1588 | |
---|
1589 | record_address_regs (XEXP (x, 0), class, 2 * scale); |
---|
1590 | break; |
---|
1591 | |
---|
1592 | case REG: |
---|
1593 | { |
---|
1594 | register struct costs *pp = &costs[REGNO (x)]; |
---|
1595 | register int i; |
---|
1596 | |
---|
1597 | pp->mem_cost += (MEMORY_MOVE_COST (Pmode) * scale) / 2; |
---|
1598 | |
---|
1599 | for (i = 0; i < N_REG_CLASSES; i++) |
---|
1600 | pp->cost[i] += (may_move_cost[i][(int) class] * scale) / 2; |
---|
1601 | } |
---|
1602 | break; |
---|
1603 | |
---|
1604 | default: |
---|
1605 | { |
---|
1606 | register char *fmt = GET_RTX_FORMAT (code); |
---|
1607 | register int i; |
---|
1608 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
---|
1609 | if (fmt[i] == 'e') |
---|
1610 | record_address_regs (XEXP (x, i), class, scale); |
---|
1611 | } |
---|
1612 | } |
---|
1613 | } |
---|
1614 | |
---|
1615 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
---|
1616 | |
---|
1617 | /* Return 1 if REG is valid as an auto-increment memory reference |
---|
1618 | to an object of MODE. */ |
---|
1619 | |
---|
1620 | static |
---|
1621 | auto_inc_dec_reg_p (reg, mode) |
---|
1622 | rtx reg; |
---|
1623 | enum machine_mode mode; |
---|
1624 | { |
---|
1625 | #ifdef HAVE_POST_INCREMENT |
---|
1626 | if (memory_address_p (mode, gen_rtx (POST_INC, Pmode, reg))) |
---|
1627 | return 1; |
---|
1628 | #endif |
---|
1629 | |
---|
1630 | #ifdef HAVE_POST_DECREMENT |
---|
1631 | if (memory_address_p (mode, gen_rtx (POST_DEC, Pmode, reg))) |
---|
1632 | return 1; |
---|
1633 | #endif |
---|
1634 | |
---|
1635 | #ifdef HAVE_PRE_INCREMENT |
---|
1636 | if (memory_address_p (mode, gen_rtx (PRE_INC, Pmode, reg))) |
---|
1637 | return 1; |
---|
1638 | #endif |
---|
1639 | |
---|
1640 | #ifdef HAVE_PRE_DECREMENT |
---|
1641 | if (memory_address_p (mode, gen_rtx (PRE_DEC, Pmode, reg))) |
---|
1642 | return 1; |
---|
1643 | #endif |
---|
1644 | |
---|
1645 | return 0; |
---|
1646 | } |
---|
1647 | #endif |
---|
1648 | |
---|
1649 | #endif /* REGISTER_CONSTRAINTS */ |
---|
1650 | |
---|
1651 | /* This is the `regscan' pass of the compiler, run just before cse |
---|
1652 | and again just before loop. |
---|
1653 | |
---|
1654 | It finds the first and last use of each pseudo-register |
---|
1655 | and records them in the vectors regno_first_uid, regno_last_uid |
---|
1656 | and counts the number of sets in the vector reg_n_sets. |
---|
1657 | |
---|
1658 | REPEAT is nonzero the second time this is called. */ |
---|
1659 | |
---|
1660 | /* Indexed by pseudo register number, gives uid of first insn using the reg |
---|
1661 | (as of the time reg_scan is called). */ |
---|
1662 | |
---|
1663 | int *regno_first_uid; |
---|
1664 | |
---|
1665 | /* Indexed by pseudo register number, gives uid of last insn using the reg |
---|
1666 | (as of the time reg_scan is called). */ |
---|
1667 | |
---|
1668 | int *regno_last_uid; |
---|
1669 | |
---|
1670 | /* Indexed by pseudo register number, gives uid of last insn using the reg |
---|
1671 | or mentioning it in a note (as of the time reg_scan is called). */ |
---|
1672 | |
---|
1673 | int *regno_last_note_uid; |
---|
1674 | |
---|
1675 | /* Record the number of registers we used when we allocated the above two |
---|
1676 | tables. If we are called again with more than this, we must re-allocate |
---|
1677 | the tables. */ |
---|
1678 | |
---|
1679 | static int highest_regno_in_uid_map; |
---|
1680 | |
---|
1681 | /* Maximum number of parallel sets and clobbers in any insn in this fn. |
---|
1682 | Always at least 3, since the combiner could put that many together |
---|
1683 | and we want this to remain correct for all the remaining passes. */ |
---|
1684 | |
---|
1685 | int max_parallel; |
---|
1686 | |
---|
1687 | void |
---|
1688 | reg_scan (f, nregs, repeat) |
---|
1689 | rtx f; |
---|
1690 | int nregs; |
---|
1691 | int repeat; |
---|
1692 | { |
---|
1693 | register rtx insn; |
---|
1694 | |
---|
1695 | if (!repeat || nregs > highest_regno_in_uid_map) |
---|
1696 | { |
---|
1697 | /* Leave some spare space in case more regs are allocated. */ |
---|
1698 | highest_regno_in_uid_map = nregs + nregs / 20; |
---|
1699 | regno_first_uid |
---|
1700 | = (int *) oballoc (highest_regno_in_uid_map * sizeof (int)); |
---|
1701 | regno_last_uid |
---|
1702 | = (int *) oballoc (highest_regno_in_uid_map * sizeof (int)); |
---|
1703 | regno_last_note_uid |
---|
1704 | = (int *) oballoc (highest_regno_in_uid_map * sizeof (int)); |
---|
1705 | reg_n_sets |
---|
1706 | = (short *) oballoc (highest_regno_in_uid_map * sizeof (short)); |
---|
1707 | } |
---|
1708 | |
---|
1709 | bzero ((char *) regno_first_uid, highest_regno_in_uid_map * sizeof (int)); |
---|
1710 | bzero ((char *) regno_last_uid, highest_regno_in_uid_map * sizeof (int)); |
---|
1711 | bzero ((char *) regno_last_note_uid, |
---|
1712 | highest_regno_in_uid_map * sizeof (int)); |
---|
1713 | bzero ((char *) reg_n_sets, highest_regno_in_uid_map * sizeof (short)); |
---|
1714 | |
---|
1715 | max_parallel = 3; |
---|
1716 | |
---|
1717 | for (insn = f; insn; insn = NEXT_INSN (insn)) |
---|
1718 | if (GET_CODE (insn) == INSN |
---|
1719 | || GET_CODE (insn) == CALL_INSN |
---|
1720 | || GET_CODE (insn) == JUMP_INSN) |
---|
1721 | { |
---|
1722 | if (GET_CODE (PATTERN (insn)) == PARALLEL |
---|
1723 | && XVECLEN (PATTERN (insn), 0) > max_parallel) |
---|
1724 | max_parallel = XVECLEN (PATTERN (insn), 0); |
---|
1725 | reg_scan_mark_refs (PATTERN (insn), insn, 0); |
---|
1726 | |
---|
1727 | if (REG_NOTES (insn)) |
---|
1728 | reg_scan_mark_refs (REG_NOTES (insn), insn, 1); |
---|
1729 | } |
---|
1730 | } |
---|
1731 | |
---|
1732 | /* X is the expression to scan. INSN is the insn it appears in. |
---|
1733 | NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. */ |
---|
1734 | |
---|
1735 | static void |
---|
1736 | reg_scan_mark_refs (x, insn, note_flag) |
---|
1737 | rtx x; |
---|
1738 | rtx insn; |
---|
1739 | int note_flag; |
---|
1740 | { |
---|
1741 | register enum rtx_code code = GET_CODE (x); |
---|
1742 | register rtx dest; |
---|
1743 | register rtx note; |
---|
1744 | |
---|
1745 | switch (code) |
---|
1746 | { |
---|
1747 | case CONST_INT: |
---|
1748 | case CONST: |
---|
1749 | case CONST_DOUBLE: |
---|
1750 | case CC0: |
---|
1751 | case PC: |
---|
1752 | case SYMBOL_REF: |
---|
1753 | case LABEL_REF: |
---|
1754 | case ADDR_VEC: |
---|
1755 | case ADDR_DIFF_VEC: |
---|
1756 | return; |
---|
1757 | |
---|
1758 | case REG: |
---|
1759 | { |
---|
1760 | register int regno = REGNO (x); |
---|
1761 | |
---|
1762 | regno_last_note_uid[regno] = INSN_UID (insn); |
---|
1763 | if (!note_flag) |
---|
1764 | regno_last_uid[regno] = INSN_UID (insn); |
---|
1765 | if (regno_first_uid[regno] == 0) |
---|
1766 | regno_first_uid[regno] = INSN_UID (insn); |
---|
1767 | } |
---|
1768 | break; |
---|
1769 | |
---|
1770 | case EXPR_LIST: |
---|
1771 | if (XEXP (x, 0)) |
---|
1772 | reg_scan_mark_refs (XEXP (x, 0), insn, note_flag); |
---|
1773 | if (XEXP (x, 1)) |
---|
1774 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag); |
---|
1775 | break; |
---|
1776 | |
---|
1777 | case INSN_LIST: |
---|
1778 | if (XEXP (x, 1)) |
---|
1779 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag); |
---|
1780 | break; |
---|
1781 | |
---|
1782 | case SET: |
---|
1783 | /* Count a set of the destination if it is a register. */ |
---|
1784 | for (dest = SET_DEST (x); |
---|
1785 | GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART |
---|
1786 | || GET_CODE (dest) == ZERO_EXTEND; |
---|
1787 | dest = XEXP (dest, 0)) |
---|
1788 | ; |
---|
1789 | |
---|
1790 | if (GET_CODE (dest) == REG) |
---|
1791 | reg_n_sets[REGNO (dest)]++; |
---|
1792 | |
---|
1793 | /* If this is setting a pseudo from another pseudo or the sum of a |
---|
1794 | pseudo and a constant integer and the other pseudo is known to be |
---|
1795 | a pointer, set the destination to be a pointer as well. |
---|
1796 | |
---|
1797 | Likewise if it is setting the destination from an address or from a |
---|
1798 | value equivalent to an address or to the sum of an address and |
---|
1799 | something else. |
---|
1800 | |
---|
1801 | But don't do any of this if the pseudo corresponds to a user |
---|
1802 | variable since it should have already been set as a pointer based |
---|
1803 | on the type. */ |
---|
1804 | |
---|
1805 | if (GET_CODE (SET_DEST (x)) == REG |
---|
1806 | && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER |
---|
1807 | && ! REG_USERVAR_P (SET_DEST (x)) |
---|
1808 | && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) |
---|
1809 | && ((GET_CODE (SET_SRC (x)) == REG |
---|
1810 | && REGNO_POINTER_FLAG (REGNO (SET_SRC (x)))) |
---|
1811 | || ((GET_CODE (SET_SRC (x)) == PLUS |
---|
1812 | || GET_CODE (SET_SRC (x)) == LO_SUM) |
---|
1813 | && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT |
---|
1814 | && GET_CODE (XEXP (SET_SRC (x), 0)) == REG |
---|
1815 | && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0)))) |
---|
1816 | || GET_CODE (SET_SRC (x)) == CONST |
---|
1817 | || GET_CODE (SET_SRC (x)) == SYMBOL_REF |
---|
1818 | || GET_CODE (SET_SRC (x)) == LABEL_REF |
---|
1819 | || (GET_CODE (SET_SRC (x)) == HIGH |
---|
1820 | && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST |
---|
1821 | || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF |
---|
1822 | || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF)) |
---|
1823 | || ((GET_CODE (SET_SRC (x)) == PLUS |
---|
1824 | || GET_CODE (SET_SRC (x)) == LO_SUM) |
---|
1825 | && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST |
---|
1826 | || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF |
---|
1827 | || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF)) |
---|
1828 | || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 |
---|
1829 | && (GET_CODE (XEXP (note, 0)) == CONST |
---|
1830 | || GET_CODE (XEXP (note, 0)) == SYMBOL_REF |
---|
1831 | || GET_CODE (XEXP (note, 0)) == LABEL_REF)))) |
---|
1832 | REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1; |
---|
1833 | |
---|
1834 | /* ... fall through ... */ |
---|
1835 | |
---|
1836 | default: |
---|
1837 | { |
---|
1838 | register char *fmt = GET_RTX_FORMAT (code); |
---|
1839 | register int i; |
---|
1840 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
---|
1841 | { |
---|
1842 | if (fmt[i] == 'e') |
---|
1843 | reg_scan_mark_refs (XEXP (x, i), insn, note_flag); |
---|
1844 | else if (fmt[i] == 'E' && XVEC (x, i) != 0) |
---|
1845 | { |
---|
1846 | register int j; |
---|
1847 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
---|
1848 | reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag); |
---|
1849 | } |
---|
1850 | } |
---|
1851 | } |
---|
1852 | } |
---|
1853 | } |
---|
1854 | |
---|
1855 | /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1 |
---|
1856 | is also in C2. */ |
---|
1857 | |
---|
1858 | int |
---|
1859 | reg_class_subset_p (c1, c2) |
---|
1860 | register enum reg_class c1; |
---|
1861 | register enum reg_class c2; |
---|
1862 | { |
---|
1863 | if (c1 == c2) return 1; |
---|
1864 | |
---|
1865 | if (c2 == ALL_REGS) |
---|
1866 | win: |
---|
1867 | return 1; |
---|
1868 | GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1], |
---|
1869 | reg_class_contents[(int)c2], |
---|
1870 | win); |
---|
1871 | return 0; |
---|
1872 | } |
---|
1873 | |
---|
1874 | /* Return nonzero if there is a register that is in both C1 and C2. */ |
---|
1875 | |
---|
1876 | int |
---|
1877 | reg_classes_intersect_p (c1, c2) |
---|
1878 | register enum reg_class c1; |
---|
1879 | register enum reg_class c2; |
---|
1880 | { |
---|
1881 | #ifdef HARD_REG_SET |
---|
1882 | register |
---|
1883 | #endif |
---|
1884 | HARD_REG_SET c; |
---|
1885 | |
---|
1886 | if (c1 == c2) return 1; |
---|
1887 | |
---|
1888 | if (c1 == ALL_REGS || c2 == ALL_REGS) |
---|
1889 | return 1; |
---|
1890 | |
---|
1891 | COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); |
---|
1892 | AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); |
---|
1893 | |
---|
1894 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose); |
---|
1895 | return 1; |
---|
1896 | |
---|
1897 | lose: |
---|
1898 | return 0; |
---|
1899 | } |
---|
1900 | |
---|